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Volumn , Issue , 2010, Pages 13-22

Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing

Author keywords

FPGA; Intermediate fabrics; Placement and routing; Speedup; Virtualization

Indexed keywords

FPGA; INTERMEDIATE FABRICS; PLACEMENT AND ROUTING; SPEEDUP; VIRTUALIZATIONS;

EID: 78650654800     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1878961.1878966     Document Type: Conference Paper
Times cited : (83)

References (36)
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    • Craven, S.1    Athanas, P.2
  • 9
    • 0034174025 scopus 로고    scopus 로고
    • The density advantage of configurable computing
    • A. DeHon, "The density advantage of configurable computing, " Computer, vol. 33, no. 4, pp. 41-49, 2000.
    • (2000) Computer , vol.33 , Issue.4 , pp. 41-49
    • Dehon, A.1
  • 10
    • 34548069377 scopus 로고    scopus 로고
    • Optimized generation of memory structure in compiling window operations onto reconfigurable hardware
    • Y. Dong, Y. Dou, and J. Zhou, "Optimized generation of memory structure in compiling window operations onto reconfigurable hardware, " in ARC, 2007, pp. 110-121.
    • (2007) ARC , pp. 110-121
    • Dong, Y.1    Dou, Y.2    Zhou, J.3
  • 26
    • 78650661368 scopus 로고    scopus 로고
    • Mitrionics, Inc. The Mitrion Virtual Processor. 2010. http://www.mitrionics.com/?page=mitrion-virtual-processor.
    • (2010) The Mitrion Virtual Processor
  • 33
    • 0036857029 scopus 로고    scopus 로고
    • Energy advantages of microprocessor platforms with on-chip configurable logic
    • G. Stitt and F. Vahid, "Energy advantages of microprocessor platforms with on-chip configurable logic, " IEEE Design & Test, vol. 19, no. 6, pp. 36-43, 2002.
    • (2002) IEEE Design & Test , vol.19 , Issue.6 , pp. 36-43
    • Stitt, G.1    Vahid, F.2
  • 35
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    • Warp processing: Dynamic translation of binaries to FPGA circuits
    • July
    • F. Vahid, G. Stitt, and R. Lysecky, "Warp processing: Dynamic translation of binaries to FPGA circuits, " Computer, vol. 41, no. 7, pp. 40-46, July 2008.
    • (2008) Computer , vol.41 , Issue.7 , pp. 40-46
    • Vahid, F.1    Stitt, G.2    Lysecky, R.3
  • 36
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    • Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware
    • IET, September
    • J. Wang, Q. Chen, and C. Lee, "Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware, " Computers & Digital Techniques, IET, vol. 2, no. 5, pp. 386-400, September 2008.
    • (2008) Computers & Digital Techniques , vol.2 , Issue.5 , pp. 386-400
    • Wang, J.1    Chen, Q.2    Lee, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.