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Volumn , Issue , 2004, Pages 838-845

Simultaneous short-path and long-path timing optimization for FPGAs

Author keywords

FPGA; Routing; Timing

Indexed keywords

LONG-PATH; PERIPHERAL COMPONENT INTERCONNECT (PCI); SHORT-PATH; TIMING OPTIMIZATION;

EID: 16244420083     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382691     Document Type: Conference Paper
Times cited : (26)

References (12)
  • 3
    • 0027797124 scopus 로고
    • Minimum padding to satisfy short path constraints
    • N. Shenoy, R. Brayton, and A. Sangiovanni-Vincentelli, "Minimum Padding to Satisfy Short Path Constraints," ICCAD, 1993, pp. 156-161.
    • (1993) ICCAD , pp. 156-161
    • Shenoy, N.1    Brayton, R.2    Sangiovanni-Vincentelli, A.3
  • 4
    • 0023568910 scopus 로고
    • Circuit placement for predictable performance
    • P. S. Hauge, R. Nair, and E. J. Yoffa, "Circuit Placement for Predictable Performance", ICCAD, 1987, pp. 88-91.
    • (1987) ICCAD , pp. 88-91
    • Hauge, P.S.1    Nair, R.2    Yoffa, E.J.3
  • 5
    • 0025556064 scopus 로고
    • Timing constraints for correct performance
    • H. Youssef and E. Shragowitz, "Timing Constraints for Correct Performance", ICCAD, 1990, pp. 24-27.
    • (1990) ICCAD , pp. 24-27
    • Youssef, H.1    Shragowitz, E.2
  • 6
    • 0026962312 scopus 로고
    • Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
    • J. Frankle, "Iterative and Adaptive Slack Allocation for Performance-driven Layout and FPGA Routing", DAC, 1992, pp. 536-542.
    • (1992) DAC , pp. 536-542
    • Frankle, J.1
  • 7
    • 0029234175 scopus 로고
    • A performance and routability-driven router for FPGAs considering path delays
    • Y. S. Lee and A. Wu, "A Performance and Routability-Driven Router for FPGAs Considering Path Delays", DAC, 1995, pp. 557-561.
    • (1995) DAC , pp. 557-561
    • Lee, Y.S.1    Wu, A.2
  • 10
    • 0037389313 scopus 로고    scopus 로고
    • Timing-driven routing for FPGAs based on lagrangian relaxation
    • April
    • S. Lee and M. Wong, "Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation," IEEE TCAD, April 2003, pp. 506-511.
    • (2003) IEEE TCAD , pp. 506-511
    • Lee, S.1    Wong, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.