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Volumn , Issue , 2001, Pages 29-36
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Runtime and quality tradeoffs in FPGA placement and routing
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Author keywords
Computer aided Design; Fast CAD for FPGAs; FPGAs; Placement; Routing
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Indexed keywords
ALGORITHMS;
COMPUTER AIDED DESIGN;
QUALITY CONTROL;
ROUTERS;
TRADE-OFF ORIENTED ALGORITHMS;
FIELD PROGRAMMABLE GATE ARRAYS;
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EID: 0035007653
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/360276.360294 Document Type: Conference Paper |
Times cited : (58)
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References (13)
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