Dynamic FPGA routing for just-in-time FPGA compilation

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 954-959

  Lysecky, Roman ^a   Vahid, Frank ^a,b   Tan, Sheldon X D ^a  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Codesign; Configurable logic; Dynamic optimization; FPGA; Hardware software partitioning; Just in time compilation; Place and route; Platforms; System on a chip; Warp processors

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; JAVA PROGRAMMING LANGUAGE; LOGIC DESIGN; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; RESOURCE ALLOCATION; ROUTERS;

CONFIGURABLE LOGIC; DYNAMIC OPTIMIZATION; HARDWARE/SOFTWARE PARTITIONING; JUST-IN-TIME COMPILATION; PLACE AND ROUTE; SYSTEM-ON-A-CHIP; WARP PROCESSORS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 4444282802     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996819     Document Type: Conference Paper

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