Density advantage of configurable computing

Computer

Volumn 33, Issue 4, 2000, Pages 41-49

  DeHon, André ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; INTERCONNECTION NETWORKS; LOGIC GATES; TABLE LOOKUP;

CONFIGURABLE COMPUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034174025     PISSN: 00189162     EISSN: None     Source Type: Journal    
DOI: 10.1109/2.839320     Document Type: Article

References (19)

1. S. Knapp, Using Programmable Logic to Accelerate DSP Functions, Xilinx Inc., San Jose, Calif., Mar. 1998; http://www.xilinx.com/appnotes/dspintro.pdf.
2. M. Butts, "Future Directions of Dynamically Reprogrammable Systems," Proc. 1995 IEEE Custom Integrated Circuits Conf., IEEE CS Press, Los Alamitos, Calif., 1995, pp. 487-494.
3. I. Goldberg and D. Wagner, Architectural Considerations for Cryptanalytic Hardware, Report CS252, Univ. of California, Berkeley, 1996; http://www.es.Berkeley. edu/˜iang/isaac/hardware/.
4. P. Gronowski et al., "A 433-MHz 64b Quad-Issue RISC Microprocessor," Digest of Tech. Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE CS Press, Los Alamitos, Calif., 1996, pp. 222-223.
5. W. Tsu et al., "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," Proc. Int'l Symp. Field-Programmable Gate Arrays, IEEE CS Press, Los Alamitos, Calif., 1999, pp. 125-134.
6. A. DeHon, Reconfigurable Architectures for General-Purpose Computing, AI Tech. Report 1586, MIT Artificial Intelligence Laboratory, Cambridge, Mass., 1996.
7. J. Fadavi-Ardekani, "M × N Booth Encoded Multiplier Generator Using Optimized Wallace Trees," IEEE Trans. VLSI Systems, June 1993, pp. 120-125.
8. T. Isshiki and W.W.-M. Dai, "High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems," Proc. ACM/ SIGDA Int'l Symp. Field-Programmable Gate Arrays, ACM Press, New York, 1995, pp. 167-173.
9. K. Kaneko et al., "A 50ns DSP with Parallel Processing Architecture," Digest of Tech. Papers, 1987 Int'l Solid-State Circuits Conf., IEEE Press, Piscataway, N.J., 1987, pp. 158-159.
10. J. Yetter et al., "A15-MIPS 32b Microprocessor," Digest of Tech. Papers, 1987 Int'l Solid-State Circuits Conf., IEEE Press, Piscataway, N.J., 1987, pp. 26-27.
11. D.J. Magenheimer et al., "Integer Multiplication and Division on the HP Precision Architecture," Proc. Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems, IEEE Press, Piscataway, N.J., 1987, pp. 90-99.
12. K.D. Chapman, "Fast Integer Multipliers Fit in FPGAs," EDN, Vol. 39, No. 10, May 12, 1993, p. 80.
13. K. Nadehara, M. Hayashida, and I. Kuroda, "A Low-Power, 32-bit RISC Processor with Signal Processing Capability and Its Multiply-Adder," VLSI Signal Processing, IEEE Press, Piscataway, N.J., 1995, pp.51-60.
14. B. Newgard, "Signal Processing with Xilinx FPGAs," 1996; http://www.xilinx.com/apps/appnotes/sd_xdsp.pdf.
15. Implementing FIR Filters in FLEX Devices, Altera Corp., San Jose, Calif., 1998; http://www.altera.com/ document/an/an073.pdf.
16. P. Ruetz, "The Architectures and Design of a 20-MHz Real-Time DSP Chip Set," IEEE J. Solid-State Circuits, Apr. 1989, pp. 338-348.
17. C. Golla et al., "30MSamples/s Programmable Filter Processor," IEEE J. Solid-State Circuits, Dec. 1990, pp. 1502-1509.
18. D. Reuver and H. Klar, "A Configurable Convolution Chip with Programmable Coefficients," IEEE J. Solid-State Circuits, July 1992, pp. 1121-1123.
19. J. Laskowski and H. Samueli, "A 150-MHz 43-Tap Half-Band FIR Digital Filter in 1.2-μm CMOS Generated by Silicon Compiler," Proc. Custom Integrated Circuits Conf., IEEE Press, Piscataway, N.J., 1992, pp. 11.4.1-11.4.4.