Optimized generation of memory structure in compiling window operations onto reconfigurable hardware

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4419 LNCS, Issue , 2007, Pages 110-121

  Yazhuo, Dong ^a   Yong, Dou ^a   Jie, Zhou ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE COMPRESSION; PATTERN RECOGNITION;

MEMORY STRUCTURE; RECONFIGURABLE HARDWARE; WINDOW OPERATIONS;

PROGRAM COMPILERS;

EID: 34548069377     PISSN: 03029743     EISSN: 16113349     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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