A study of the scalability of on-chip routing for just-in-time FPGA compilation

Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005

Volumn 2005, Issue , 2005, Pages 57-62

  Lysecky, Roman ^a   Vahid, Frank ^a,b   Tan, Sheldon X D ^a  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Codesign; Configurable logic; Dynamic optimization; FPGA; Hardware software partitioning; Just in time (JIT) compilation; Place and route; Platforms; Standard hardware binary; System on a chip; Warp processors

Indexed keywords

CODESIGN; CONFIGURABLE LOGIC; DYNAMIC OPTIMIZATION; HARDWARE/SOFTWARE PARTITIONING; JUST-IN-TIME (JIT) COMPILATION; PLACE AND ROUTE; PLATFORMS; STANDARD HARDWARE BINARY; SYSTEM-ON-A-CHIP; WARP PROCESSORS;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; PROGRAM COMPILERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746121535     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2005.12     Document Type: Conference Paper

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