A VLIW low power Java processor for embedded applications

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 157-162

  Beck, Antonio Carlos S ^a   Carro, Luigi ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Java; Power consumption; VLIW

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTER SIMULATION; DATA PROCESSING; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; JAVA PROGRAMMING LANGUAGE; PERSONAL DIGITAL ASSISTANTS;

BYTECODES; JAVA MACHINES; JAVA PROCESSORS; VLIW;

PROGRAM PROCESSORS;

EID: 14244258448     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016568.1016614     Document Type: Conference Paper

References (24)

1. Schlett, M. Trends in Embedded-Microprocessor Design. In Computer, vol. 31, n. 8, 1998, 44-49
2. Takahashi, D. Java Chips Make a Comeback. In Red Herring, 2001
3. Lawton, G. Moving Java into Mobile Phones. In Computer, vol. 35, n. 6, 2002, 17-20
4. Tiwari, V., Malik, S., Wolfe, A. Power Analysis of Embedded Software: A First Step Towards Software Power Minimization. In IEEE Transactions on VLSI Systems, vol. 2, n. 4, Dec. 1994, 437-445
5. Chen, G., Shetty, R., Kandemir, M., Vijaykrishnan, N., Irwin, M. Tuning garbage collection for reducing memory system energy in an embedded Java environment. In ACM Transactions on Embedded Computing Systems, vol. 1, n. 1, Nov. 2002, 27-55
6. O'Connor, J. M., Tremblat, M. Picojava-I: the Java Virtual Machine in Hardware. In IEEE Micro, vol. 17, n. 2, Mar-Apr. 1997, 45-53
7. Sun Microsystems. In PicoJava-II Microarchitecture Guide, Mar. 1999
8. Kreuzinger, J., Marston, R., Ungerer, Th., Brinkschulte, U., Krakowski, C. The Komodo Project: Thread-based Event Handling Supported by a Multithreaded Java Microcontroller. In 25th Euromicro Conference, Sep. 1999, 2122-2128
9. Nakamura, K., Sakai, K., Ae, T. Real-Time Multimedia Data Processing using VLIW Hardware Stack Processor, In Proceedings IEEE Workshop on Parallel and Distributed Real-Time Systems, 1995, 84-89
10. Tremblay, M., Chan, J., Chaudhry, S., Conigliaro, A., Tse, S. The MAJC Architecture: A Synthesis of Parallelism and Scalability. In IEEE Micro, vol. 20, n. 6, 2000, 12-25
11. Gray, J., Naylor, A., Abnous, A., Bagherzadeh, N. VIPER: A 25MHz, 100 MIPS Peak VLIW Microprocessor. In Proceedings of the 1993 IEEE Custom Integrated Circuits Conference, San Diego, 1993.
12. Suga, A., Matsunami, K. Introducing the FR500 embedded microprocessor. In IEEE Micro, Jul-Aug. 2000, 21-27
13. Seshan, N. High VelociTI Processing. In IEEE Signal Processing Magazine, vol. 15, n.2, March 1998, 86-101
14. Ito, S.A., Carro, L., Jacobi, R.P. Making Java Work for Microcontroller Applications. In IEEE Design & Test of Computers, vol. 18, n. 5, 2001, 100-110
15. Beck, A.C.S., Carro, L. Low Power Java Processor for Embedded Applications. In: IFIP 12th International Conference on Very Large Scale Integration, Germany, December (2003)
16. Hennessy, J. L., Patterson, D. A. Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 3th edition, 2003
17. Beck, A.C.S., Mattos, J.C.B., Wagner, F.R., Carro, L. CACO-PS: A General Purpose Cycle-Accurate Configurable Power-Simulator. In 16th Brazilian Symp. Integrated Circuit Design (SBCCI 2003), Sep. 2003
18. Chen, R., Irwin, M. J., Bajwa, R. Architecture-Level Power Estimation and Design Experiments. In ACM Transactions on Design Automation of Electronic Systems, vol. 6, n. 1, Jan. 2001, 50-66
19. Leonardo Spectrum, available at homepage: http://www.mentor.com/synthesis
20. Pouwelse, J., Langendown, K., Sips, H. Dynamic Voltage Scaling on a Low-Power Microprocessor. In The Seventh Annual International Conference on Mobile Computing and Networking, 2001, 251-259
21. Transmeta Corporation, Tm5400 processor specifications, http://www.transmeta.com
22. Montanaro J. and et. al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. In IEEE Journal of Solid-State Circuits, vol. 31, n. 11, Nov. 1996, 1703-1714
23. Inoue, K., Ishihara, T., Murakami, K. Way-predicting set-associative cache for high performance and low energy consumption. In Proceedings on Low Power Electronics and Design, Aug. 1999, pp. 273-275
24. Lee, M., Tirumalai, P., Ngai, T. Software Pipelining and Superblock Scheduling: Compilation Techniques for VLIW Machines. In Proceedings of the 26th Hawaii International Conference on System Sciences, Jan. 1993