-
1
-
-
33745791682
-
On Improving Best-Effort throughput by better utilization of Guaranteed-Throughput channels in an on-chip communication system
-
D. Andreasson and S. Kumar. On Improving Best-Effort throughput by better utilization of Guaranteed-Throughput channels in an on-chip communication system. In Proceeding of 22th IEEE Norchip Conference, 2004.
-
(2004)
Proceeding of 22th IEEE Norchip Conference
-
-
Andreasson, D.1
Kumar, S.2
-
2
-
-
78650646928
-
-
AMBA 3 AXI overview, 2005. http://www.arm.com/products/system-ip/ interconnect/axi/index.php.
-
(2005)
AMBA 3 AXI Overview
-
-
-
3
-
-
78650640812
-
-
ARM AMBA 2.0 AHB-APB Overview, 2005. http://www.arm.com/products/system- ip/interconnect/amba-design-kit.php.
-
(2005)
ARM AMBA 2.0 AHB-APB Overview
-
-
-
4
-
-
22344451866
-
MPARM: Exploring the multi-processor SoC design space with systemc
-
September
-
L. Benini, D. Bertozzi, A. Bogliolo, F. Menichelli, and M. Olivieri. MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. The Journal of VLSI Signal Processing, 41(2):169-182, September 2005.
-
(2005)
The Journal of VLSI Signal Processing
, vol.41
, Issue.2
, pp. 169-182
-
-
Benini, L.1
Bertozzi, D.2
Bogliolo, A.3
Menichelli, F.4
Olivieri, M.5
-
5
-
-
0036149420
-
Networks on Chips: A new SoC paradigm
-
January
-
L. Benini and G. De Micheli. Networks on Chips: A new SoC Paradigm. IEEE Computer, 35(1):70 - 78, January 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
8
-
-
27344444925
-
A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip
-
DOI 10.1109/DATE.2005.36, 1395761, Proceedings - Design, Automation and Test in Europe, DATE '05
-
T. Bjerregaard and J. Sparso. A Router Architecture for Connection-Oriented Service Guarantees in the. MANGO Clockless Network-on-Chip. In Proc. Design, Automation and Test in Europe, pages 1226-1231, 2005. (Pubitemid 44172177)
-
(2005)
Proceedings -Design, Automation and Test in Europe, DATE '05
, vol.II
, pp. 1226-1231
-
-
Bjerregaard, T.1
Sparso, J.2
-
9
-
-
1242309790
-
QNoC: QoS Architecture and design process for network on chip
-
E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. QNoC: QoS Architecture and Design Process for Network on Chip. Journal of System Architecture, 50:105-128, 2004.
-
(2004)
Journal of System Architecture
, vol.50
, pp. 105-128
-
-
Bolotin, E.1
Cidon, I.2
Ginosar, R.3
Kolodny, A.4
-
11
-
-
70450031266
-
Implementing OpenMP on a high performance embedded multicore MPSoC
-
B. Chapman, L. Huang, E. Biscondi, E. Stotzer, A. Shrivastava, and A. Gatherer. Implementing OpenMP on a High Performance Embedded Multicore MPSoC. In IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, pages 1-8, 2009.
-
(2009)
IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
, pp. 1-8
-
-
Chapman, B.1
Huang, L.2
Biscondi, E.3
Stotzer, E.4
Shrivastava, A.5
Gatherer, A.6
-
13
-
-
0026825968
-
Virtual-channel flow control
-
Mar.
-
W. J. Dally. Virtual-Channel Flow Control. IEEE Trans. Parallel Distrib. Syst., 3(2):194-205, Mar. 1992.
-
(1992)
IEEE Trans. Parallel Distrib. Syst.
, vol.3
, Issue.2
, pp. 194-205
-
-
Dally, W.J.1
-
15
-
-
33749316145
-
A new protocol stack model for network on chip
-
volume 00, Mar. 2-3
-
M. Dehyadgari, M. Nickray, A. Afzali-kusha, and Z. Navabi. A New Protocol Stack Model for Network on Chip. In Proc. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, volume 00, page 3pp., Mar. 2-3, 2006.
-
(2006)
Proc. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
, pp. 3
-
-
Dehyadgari, M.1
Nickray, M.2
Afzali-Kusha, A.3
Navabi, Z.4
-
16
-
-
33646144623
-
The OpenMP source code repository
-
Feb.
-
A. Dorta, C. Rodriguez, and F. de Sande. The OpenMP Source Code Repository. In Parallel, Distributed and Network-Based Processing, 2005. PDP 2005. 13th Euromicro Conference on, pages 244-250, Feb. 2005.
-
(2005)
Parallel, Distributed and Network-Based Processing, 2005. PDP 2005. 13th Euromicro Conference on
, pp. 244-250
-
-
Dorta, A.1
Rodriguez, C.2
De Sande, F.3
-
18
-
-
84893737717
-
Networks on silicon: Combining best-effort and guaranteed services
-
Mar. 4-8
-
K. Goossens, J. van Meerbergen, A. Peeters, and R. Wielage. Networks on Silicon: Combining Best-Effort and Guaranteed Services. In Proc. Design, Automation and Test in Europe Conference and Exhibition, pages 423-425, Mar. 4-8, 2002.
-
(2002)
Proc. Design, Automation and Test in Europe Conference and Exhibition
, pp. 423-425
-
-
Goossens, K.1
Van Meerbergen, J.2
Peeters, A.3
Wielage, R.4
-
20
-
-
70350053280
-
Aelite: A flit-synchronous network on chip with composable and predictable services
-
Apr. 20-24
-
A. Hansson, M. Subburaman, and K. Goossens. Aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services. In Proc. DATE '09. Design, Automation. Test in Europe Conference. Exhibition, pages 250-255, Apr. 20-24, 2009.
-
(2009)
Proc. DATE '09. Design, Automation. Test in Europe Conference. Exhibition
, pp. 250-255
-
-
Hansson, A.1
Subburaman, M.2
Goossens, K.3
-
21
-
-
68849090533
-
Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis
-
Sept.
-
A. Hansson, M. Wiggers, A. Moonen, K. Goossens, and M. Bekooij. Enabling Application-Level Performance Guarantees in Network-Based Systems on Chip by Applying Dataflow Analysis. IET Computers Digital Techniques, 3(5):398-412, Sept. 2009.
-
(2009)
IET Computers Digital Techniques
, vol.3
, Issue.5
, pp. 398-412
-
-
Hansson, A.1
Wiggers, M.2
Moonen, A.3
Goossens, K.4
Bekooij, M.5
-
22
-
-
50149096693
-
A low cost network-on-chip with guaranteed service well suited to the GALS approach
-
I. Miro Panades, A. Greiner., A.Sheibanyrad. A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. In Nano-Net 2006, 2006.
-
(2006)
Nano-Net 2006
-
-
Panades, I.M.1
Greiner, A.2
Sheibanyrad, A.3
-
24
-
-
34547209372
-
Programming models and HW-SW interfaces abstraction for multi-processor SoC
-
New York, NY, USA, ACM
-
A. A. Jerraya, A. Bouchhima, and F. Pétrot. Programming Models and HW-SW Interfaces Abstraction for Multi-Processor SoC. In DAC '06: Proceedings of the 43rd annual Design Automation Conference, pages 280-285, New York, NY, USA, 2006. ACM.
-
(2006)
DAC '06: Proceedings of the 43rd Annual Design Automation Conference
, pp. 280-285
-
-
Jerraya, A.A.1
Bouchhima, A.2
Pétrot, F.3
-
25
-
-
46649083626
-
Effective OpenMP implementation and translation for multiprocessor system-on-chip without using OS
-
Jan. 23-26
-
W.-C. Jeun and S. Ha. Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS. In Proc. Asia and South Pacific Design Automation Conference ASP-DAC '07, pages 44-49, Jan. 23-26, 2007.
-
(2007)
Proc. Asia and South Pacific Design Automation Conference ASP-DAC '07
, pp. 44-49
-
-
Jeun, W.-C.1
Ha, S.2
-
26
-
-
38349178746
-
Parallel programming of multi-processor SoC: A HW-SW interface perspective
-
L. Kriaa, A. Bouchhima, M. Gligor, A. Fouillart, F. Pétrot, and A. Jerraya. Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective. International Journal of Parallel Programming, 36(1):68-92, 2008.
-
(2008)
International Journal of Parallel Programming
, vol.36
, Issue.1
, pp. 68-92
-
-
Kriaa, L.1
Bouchhima, A.2
Gligor, M.3
Fouillart, A.4
Pétrot, F.5
Jerraya, A.6
-
29
-
-
2342620693
-
The Nostrum backbone- A communication protocol stack for networks on chip
-
M. Millberg, E. Nilsson, R. Thid, S. Kumar, and A. Jantsch. The Nostrum backbone-a communication protocol stack for Networks on Chip. In Proc. 17th International Conference on VLSI Design, pages 693-696, 2004.
-
(2004)
Proc. 17th International Conference on VLSI Design
, pp. 693-696
-
-
Millberg, M.1
Nilsson, E.2
Thid, R.3
Kumar, S.4
Jantsch, A.5
-
31
-
-
34047123275
-
A methodology for mapping multiple use-cases onto networks on chips
-
Mar. 6-10
-
S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli. A Methodology for Mapping Multiple Use-Cases onto Networks on Chips. In Proc. Design, Automation and Test in Europe DATE '06, volume 1, pages 1-6, Mar. 6-10, 2006.
-
(2006)
Proc. Design, Automation and Test in Europe DATE '06
, vol.1
, pp. 1-6
-
-
Murali, S.1
Coenen, M.2
Radulescu, A.3
Goossens, K.4
De Micheli, G.5
-
32
-
-
46149088969
-
Designing application-specific networks on chips with floorplan information
-
S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo. Designing Application-Specific Networks on Chips with Floorplan Information. In ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pages 355-362, 2006.
-
(2006)
ICCAD '06: Proceedings of the 2006 IEEE/ACM International Conference on Computer-aided Design
, pp. 355-362
-
-
Murali, S.1
Meloni, P.2
Angiolini, F.3
Atienza, D.4
Carta, S.5
Benini, L.6
De Micheli, G.7
Raffo, L.8
-
33
-
-
43849085367
-
Supporting OpenMP on cell
-
K. OBrien, K. OBrien, Z. Sura, T. Chen, and T. Zhang. Supporting OpenMP on Cell. International Journal of Parallel Programming, 36(3):289-311, 2008.
-
(2008)
International Journal of Parallel Programming
, vol.36
, Issue.3
, pp. 289-311
-
-
Obrien, K.1
Obrien, K.2
Sura, Z.3
Chen, T.4
Zhang, T.5
-
34
-
-
33646939186
-
-
OCP International Partnership (OCP-IP). Open Core Protocol Standard, 2003. http://www.ocpip.org/home.
-
(2003)
Open Core Protocol Standard
-
-
-
36
-
-
36849004429
-
Bringing NoCs to 65 nm
-
Sept.
-
A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. De Micheli, and L. Benini. Bringing NoCs to 65 nm. IEEE Micro, 27(5):75-85, Sept. 2007.
-
(2007)
IEEE Micro
, vol.27
, Issue.5
, pp. 75-85
-
-
Pullini, A.1
Angiolini, F.2
Murali, S.3
Atienza, D.4
De Micheli, G.5
Benini, L.6
-
37
-
-
84893753441
-
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
-
E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander. Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. In Proc. Design, Automation and Test in Europe Conference and Exhibition, pages 350-355, 2003.
-
(2003)
Proc. Design, Automation and Test in Europe Conference and Exhibition
, pp. 350-355
-
-
Rijpkema, E.1
Goossens, K.G.W.2
Radulescu, A.3
Dielissen, J.4
Meerbergen, J.V.5
Wielage, P.6
Waterlander, E.7
-
38
-
-
0034846659
-
Addressing the system-on-a-chip interconnect woes through communication-based design
-
M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. In Proc. Design Automation Conference, pages 667-672, 2001.
-
(2001)
Proc. Design Automation Conference
, pp. 667-672
-
-
Sgroi, M.1
Sheets, M.2
Mihal, A.3
Keutzer, K.4
Malik, S.5
Rabaey, J.6
Sangiovanni-Vincentelli, A.7
-
39
-
-
27344431958
-
Xpipes lite: A synthesis oriented design library for networks on chips
-
DOI 10.1109/DATE.2005.1, 1395755, Proceedings - Design, Automation and Test in Europe, DATE '05
-
S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, and G. De Micheli. ×pipes Lite: A Synthesis Oriented Design Library for Networks on Chips. In Proc. Design, Automation and Test in Europe, pages 1188-1193, 2005. (Pubitemid 44172171)
-
(2005)
Proceedings -Design, Automation and Test in Europe, DATE '05
, vol.II
, pp. 1188-1193
-
-
Stergiou, S.1
Angiolini, F.2
Carta, S.3
Raffo, L.4
Bertozzi, D.5
De Micheli, G.6
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