A new protocol stack model for network on chip

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 440-441

  Dehyadgari, Masood ^a   Nickray, Mohsen ^a   Afzali kusha, Ali ^a   Navabi, Zainalabedin ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ON CHIPS; PACKET SWITCHED COMMUNICATION PROTOCOLS; PROTOCOL STACK MODELS;

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; NETWORK PROTOCOLS; PACKET NETWORKS; REUSABILITY; TELECOMMUNICATION LINKS; TELECOMMUNICATION TRAFFIC;

MICROPROCESSOR CHIPS;

EID: 33749316145     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.7     Document Type: Conference Paper

References (5)

1. OSI 7 layers reference Model for Network Communicauon:http://www.javvin. com/osimodel.html, retrieved on Nov. 2005.
2. PCI Special Interest Group, "PCI Express Base Specification Revision 1.0a," Apr 2003.
3. D. Mayhew and V. Krishnan, "PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects," Proceedings of the 11 the Symposium on High Performance Interconnects (HOTI'03), pp.21-29, Jun. 2003.
4. H. Zimmer, A. Jantsch, Fault Modelling and Error-Control Coding in a Network-on-Chip, Master Thesis, Royal Institute of Technology (KTH), Sweden, 2002.
5. Philip Koopman, Tridib Chakravarty, "Cyclic Redundancy Code (CRC) Polynomial Selection For Embedded Networks," The International Conference on Dependable Systems and Networks, pp.145-154, Jul. 2004.