8-Gb/s source-synchronous I/O Link with adaptive receiver equalization, offset cancellation, and clock de-skew

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 80-87

  Jaussi, James E ^a   Balamurugan, Ganesh ^a   Johnson, David R ^a   Casper, Bryan ^a   Martin, Aaron ^a   Kennedy, Joseph ^a   Shanbhag, Naresh ^b   Mooney, Randy ^a  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Adaptive equalizers; Analog equalization; High speed I O; Offset cancellation; Transceivers; Waveform capture

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FILTERS; EQUALIZERS; INPUT OUTPUT PROGRAMS; OPTIMIZATION; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION LINKS; TRANSCEIVERS;

ADAPTIVE EQUALIZERS; ANALOG EQUALIZATION; HIGH-SPEED I/O; OFFSET CANCELLATION; WAVEFORM CAPTURE;

DATA COMMUNICATION SYSTEMS;

EID: 11944257220     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.838009     Document Type: Conference Paper

References (10)

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