CMOS transceiver with baud rate clock recovery for optical interconnects

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 410-413

  Emami Neyestanak, Azita ^a   Palermo, Samuel ^a   Lee, Hae Chang ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Baud rate; Clock and data recovery; Double sampling; I O; Integrating receiver; Optical interconnects; VCSEL

Indexed keywords

BAUD RATE; CLOCK AND DATA RECOVERY (CDR); DOUBLE SAMPLING; I/O; INTEGRATING RECEIVERS; VCSEL;

AMPLIFIERS (ELECTRONIC); ELECTRIC POTENTIAL; LIGHT TRANSMISSION; OPTICAL INTERCONNECTS; OSCILLATORS (ELECTRONIC); SAMPLING; SEMICONDUCTOR QUANTUM WELLS; TRANSCEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 4544353898     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. A. Emami-Neyestanak et al. "A 1.6Gb/s, 3mW CMOS Receiver for Optical Communication," in Proc. IEEE VLSI Circuits Symp., pp. 84-87, June 2002.
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7. M. E. Lee et al. "A second-order semi-digital clock recovery circuit based on injection locking", ISSCC Digest of Technical Papers, pp 1-8, Feb. 9-13, 2003