A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2885-2898

  Bulzacchelli, John F ^a,b   Meghelli, Mounir ^b   Rylov, Sergey V ^a,b   Rhee, Woogeun ^a,b   Rylyakov, Alexander V ^b   Ainspan, Herschel A ^b   Parker, Benjamin D ^b   Beakes, Michael P ^a,b   Chung, Aichin ^b   Beukema, Troy J ^b   Pepeljugoski, Petar K ^a,b   Shan, Lei ^a,b   Kwark, Young H ^a,b   Gowda, Sudhir ^a,b   Friedman, Daniel J ^a,b  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Adaptive equalizer; Decision feedback equalizer; Feed forward equalizer; Serial link; Transceiver

Indexed keywords

CHANNEL LOSS; CHIP TO CHIP COMMUNICATIONS; DECISION FEEDBACK EQUALIZER (DFE); FEED FORWARD EQUALIZER; JITTER CLOCKS;

BIT ERROR RATE; CHANNEL CAPACITY; DATA TRANSFER; EQUALIZERS; FEEDBACK CONTROL; TIMING JITTER; TRANSCEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 33845682879     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884342     Document Type: Conference Paper

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