A 4.8 GS/s 5-bit ADC-based receiver with embedded DFE for signal equalization

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 3, 2009, Pages 901-915

  Varzaghani, Aida ^a   Yang, Chih Kong Ken ^b  

^a NetLogic Microsystems Inc   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital converter (ADC); Decision feedback equalizer (DFE); Digital reference calibration; Equalization; Incomplete settling; Pipeline; Time interleaved

Indexed keywords

ANALOG-TO-DIGITAL CONVERTER (ADC); DECISION FEEDBACK EQUALIZER (DFE); DIGITAL REFERENCE CALIBRATION; EQUALIZATION; INCOMPLETE SETTLING; TIME INTERLEAVED;

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CMOS INTEGRATED CIRCUITS; CONTROL THEORY; FEEDBACK; FREQUENCY CONVERTERS; PIPELINES; SIGNAL RECEIVERS;

MULTICARRIER MODULATION;

EID: 61449198704     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2013765     Document Type: Article

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