A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-Tap DFE using soft decisions

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 881-888

  Wong, Koon Lun Jackie ^b   Rylyakov, Alexander ^c   Yang, Chih Kong Ken ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Decision feedback equalizer (DFE); Equalizer; I O link; Low power; Receiver

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SYSTEMS; ERROR DETECTION; SIGNAL RECEIVERS; TIMING CIRCUITS;

ANALOG SAMPLING; ERROR RATES; I/O LINK; TIMING CRITICAL FEEDBACK PATH;

DECISION FEEDBACK EQUALIZERS;

EID: 33947663612     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892189     Document Type: Article

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