Gate oxide reliability for nano-scale CMOS

2006 25th International Conference on Microelectronics, MIEL 2006 - Proceedings

Volumn , Issue , 2006, Pages 78-83

  Stathis, J H ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC PROPERTIES OF SOLIDS; ELECTRIC FIELDS; FAILURE (MECHANICAL); MICROELECTRONICS; MOSFET DEVICES; NANOTECHNOLOGY;

FAILURE MECHANISM; GATE OXIDE; GATE OXIDE RELIABILITY; HIGH ELECTRIC FIELDS; NANO-SCALE CMOS; NANOMETER DIMENSIONS; NEGATIVE BIAS INSTABILITIES;

GATES (TRANSISTOR);

EID: 77956535012     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMEL.2006.1650900     Document Type: Conference Paper

References (38)

1. J. H. Stathis and D. J. DiMaria, " Reliability projection for ultra-thin oxides at low voltage," Digest of the 1998 International Electron Devices Meeting, pp. 167-170, 1998.
2. R. Degraeve, B. Kaczer, and G. Groeseneken, " Reliability: a possible showstopper for oxide thickness scaling?," Semicond. Sci. Technol., vol.15, pp. 436-444, 2000.
3. 2 Interface - 4, vol.2000-2, H. Z. Massoud, I. J. R. Baumvol, M. Hirose, and E. H. Poindexter, Eds. Pennington, NJ: The Electrochemical Society, 2000, pp. 365-376.
4. J. H. Stathis, " Reliability limits for the gate insulator in CMOS technology," IBM J. Res. Develop., vol.46, pp. 265- 286, 2002.
5. E. Y. Wu, E. J. Nowak, A. Vayshenker, W. L. Lai, and D. Harmon, " CMOS scaling beyond the 100-nm node with sili- con-dioxide-based gate dielectrics," IBM J. Res. Develop., vol.46, pp. 287-298, 2002.
6. J. H. Stathis, B. P. Linder, R. Rodríguez, and S. Lombardo, " Reliability of ultra-thin oxides in CMOS circuits," Microelectron. Reliab., vol.43, p. 1353, 2003.
7. E. Y. Wu et al., " Voltge-dependent voltage-acceleration of oxide breakdown for ultra-thin oxides," Digest of the 2000 International Electron Devices Meeting, pp. 541-544, 2000.
8. S. Lombardo et al., " Dielectric breakdown mechanisms in gate oxides," J. Appl. Phys., vol.98, pp. 121301-121335, 2005.
9. J. H. Stathis, R. Rodríguez, and B. P. Linder, " Circuit implications of gate oxide breakdown," Microelectron. Reliab., vol.43, pp. 1193-1197, 2003.
10. E. Wu, J. Suñ é , B. P. Linder, J. H. Stathis, and W. L. Lai, " Critical assessment of soft breakdown stability time and the implementation of new post-breakdown methodology for ultra- thin gate oxides," Digest of the 2003 International Electron Devices Meeting, pp. 319-322, 2003.
11. F. Monsieur et al., " A thorough investigation of progressive breakdown in ultra-thin oxides. Physical understanding and application for industrial reliability assessment.," 2002 International Reliability Physics Symposium Proceedings, pp. 45-54, 2002.
12. T. Hosoi, P. Lo Re, Y. Kamakura, and K. Taniguchi, " A new model of time evolution of gate oxide leakage current after soft breakdown in ultra-thin gate oxides," Digest of the 2002 International Electron Devices Meeting, pp. 155-158, 2002.
13. B. P. Linder, S. Lombardo, J. H. Stathis, A. Vayshenker, and D. J. Frank, " Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics," IEEE Electron Device Lett., vol.23, pp. 661-663, 2002.
14. J. S. Suehle, B. Zhu, Y. Chen, and J. B. Bernstein, " Detailed study and projection of hard breakdown evolution in ultrathin gate oxides," Microelectron. Reliab., vol.45, pp. 419- 426, 2005.
15. B. Kaczer, R. Degraeve, R. O'Connor, P. Roussel, and G. Groeseneken, " Implications of progressive wear-out for lifetime extrapolation of ultra-thin (EOT∼ 1nm) SiON films," Digest of the 2004 International Electron Devices Meeting, pp. 713-716, 2004.
16. R. Rodríguez et al., " The impact of gate oxide breakdown on SRAM stability," IEEE Electron Device Lett., vol.23, pp. 559-561, 2002.
17. R. Rodríguez, J. H. Stathis, and B. P. Linder, " A model for gate oxide breakdown in CMOS inverters," IEEE Electron Device Lett., vol.24, pp. 114-116, 2003.
18. R. Rodríguez, J. H. Stathis, and B. P. Linder, " Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters," 2003 International Reliability Physics Symposium Proceedings, pp. 11-16, 2003.
19. B. P. Linder et al., " Gate oxide breakdown under current limited constant voltage stress," Digest of the 2000 Symposium on VLSI Technology, pp. 214-215, 2000.
20. K. Mueller, S. S. Gupta, S. Pae, M. Agostinelli, and P. Aminzadeh, " 6-T cell circuit dependent GOX SBD model for accurate prediction of observed Vccmin test voltage dependency," 2004 International Reliability Physics Symposium Proceedings, pp. 426-429, 2004.
21. 2 studied by the post-breakdown resistance statistics," IEEE Trans. Electron Devices, vol.47, pp. 741- 745, 2000.
22. K. Okada, " The gate oxide lifetime limited by 'B-mode' stress induced leakage current and the scaling limit of silicon dioxides in the direct tunneling regime," Semicond. Sci. Technol., vol.15, pp. 478-484, 2000.
23. R. Degraeve, B. Kaczer, A. De Keersgeiter, and G. Groeseneken, " Relation between breakdown mode and breakdown location in short channel nMOSFETs and its impact on reliability specifications," 2001 International Reliability Physics Symposium Proceedings, pp. 360-366, 2001.
24. B. Weir, M. A. Alam, P. J. Silverman, and Y. Ma, " Low voltage gate dielectric reliability," in Semiconductor Silicon/ 2002, vol.2002-2, H. R. Huff, L. Fabry, and S. Kishino, Eds. Pennington, New Jersey: The Electrochemical Society, Inc, 2002, pp. 365-374.
25. J. Suñ é , E. Wu, and W. Lai, " Limits of the successive breakdown statistics to assess chip reliability," Microelectronic Engineering, vol.72, pp. 39-44, 2004.
26. B. Kaczer et al., " Impact of MOSFET oxide breakdown on digital circuit operation and reliability," Digest of the 2000 International Electron Devices Meeting, pp. 553-556, 2000.
27. J. H. Stathis, " Gate oxide reliability for nano-scale CMOS," Proc. International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 127-130, 2005.
28. J. H. Stathis and S. Zafar, " The negative bias temperature instability in MOS devices: A review," Microelectron. Reliab., 2006.
29. Y. Miura and Y. Matukura, " Investigation of silicon-silicon dioxide interface using MOS structure," Jpn. J. Appl. Phys., vol.5, p. 180, 1966.
30. N. Kimizuka et al., " NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10μm gate CMOS generation," Digest of the 2000 Symposium on VLSI Technology, pp. 92-93, 2000.
31. Y. Mitani, M. Nagamine, H. Satake, and A. Toriumi, " NBTI mechanism in ultra-thin gate dielectric: Nitrogen-originated mechanism in SiON," Digest of the 2002 International Electron Devices Meeting, pp. 509-512, 2002.
32. J. H. Stathis, G. LaRosa, and A. Chou, " Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide," 2004 International Reliability Physics Symposium Proceedings, pp. 1-7, 2004.
33. V. Huard et al., " A thorough investigation of MOSFETs NBTI degradation," Microelectron. Reliab., vol.45, pp. 83- 98, 2005.
34. P. E. Nicollian et al., " Low voltage stress-induced-leakagecurrent in ultrathin gate oxides," 1999 International Reliability Physics Symposium Proceedings, pp. 400-404, 1999.
35. A. Ghetti, E. Sangiorgi, J. Bude, T. Sorsch, and G. Weber, " Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradation," Digest of the 1999 International Electron Devices Meeting, pp. 731-734, 1999.
36. N. Kimizuka et al., " The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling," Digest of the 1999 Symposium on VLSI Technology, pp. 73-74, 1999.
37. F. Crupi et al., " On the role of interface states in low-voltage leakage currents of metal-oxide-semiconductor structures," J. Appl. Phys., vol.80, pp. 4597-4599, 2002.
38. J. H. Stathis et al., " Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates," Microelectronic Engineering, vol.80, pp. 126-129, 2005.