Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters

IEEE International Reliability Physics Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages 11-16

  Rodriguez R ^a,b   Stathis, J H ^b   Linder, B P ^b  

^a UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^b IBM RESEARCH   (United States)

Author keywords

CMOS; Dielectric breakdown; Hard breakdown; Leakage currents; Oxide breakdown; Oxide reliability

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; RECONFIGURABLE HARDWARE; RELIABILITY; STATIC RANDOM ACCESS STORAGE; TIMING CIRCUITS;

CAPACITOR STRUCTURES; DIFFUSION LEAKAGE; EXPERIMENTAL VERIFICATION; GATE OXIDE BREAKDOWN; HARD BREAKDOWN; OXIDE BREAKDOWN; OXIDE RELIABILITY; POWER LAW FORMULA;

LEAKAGE CURRENTS;

EID: 84955296083     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197713     Document Type: Conference Paper

References (17)

1. H. Stathis and D. J. DiMaria, "Reliability projection for ultrathin oxides a¯t low voltage," in IEDM Tech. Dig., 1998, pp. 167-170
2. R. Degraeve, B. Kaczer, and O. Groeseneken, "Reliability: a possible showstopper for oxide thickness scaling?," Semicond. Sci. Technol., vol. 15, 2000, pp. 436-444.
3. B. Kaczer, R. Degraeve, G. Groeseneken, M. Rasras, S. Kubicek, E. Vandamme and G. Badenes, "Impact of MOSFET oxide breakdown on digital circuit operation and reliability," in IEDM Tech. Dig., 2000, pp. 553-556.
4. R. Rodriguez, J. H. Stathis, B. P. Linder, S. Kowalczyk, C. T. Chuang, R. V. Joshi, G. Northrop, K. Bernstein, A. J. Bhavnagarwala and S. Lombardo, "The impact of gate oxide breakdown on SRAM stability", IEEE Electron Device Lett. vol. 23, No. 9, 2002, pp. 559-561.
5. F. Monsieur, E. Vincent, D. Roy, S. Bruyere, J. C. Vildeuil, G. Pananakakis, G. Ghibaudo, "A thorough investigation of progressive breakdown in ultra-thin oxides. Physical understanding and application for industrial reliability assessment", IRPS Proc. 2002, pp. 45-54.
6. B. P. Linder, S. Lombardo, J. H. Stathis, A. Vayshenker and D. J. Frank, "Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics", IEEE Electron Device Lett., vol. 23, No. 11, 2002, pp. 661-663.
7. P. Smeys, et al., "A high performance 0.13μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric," VLSI Tech. Symp., 2000, pp. 184-185.
8. B. P. Linder, J. H. Stathis, R. A. Wachnik, E. Wu, S. A. Cohen, A. Ray and A. Vayshenker, "Gate oxide breakdown under current limited constant voltage stress", VLSI Technol. Symp. Dig., 2000, pp. 214-215.
9. D. J. DiMaria and J. W. Stasiak, "Trap creation in silicon dioxide produced by hot electrons", J. Appl. Phys. vol. 65, No. 6, 1989, pp. 2342-2356.
10. E. Miranda, J. Suñé, R. Rodriguez, M. Nafria, and X. Aymerich, "A function-fit model for the soft breakdown failure mode," IEEE Electron Device Lett., vol. 20, 1999, pp. 265-267.
11. K. N. Quader, C. C. Li, R. Tu, E. Rosenbaum, P. K. Ko, C. Hu, "A bi-directional NMOSFET current reduction model for simulation of hot-carrier induced circuit degradation", IEEE Trans. Electron Devices, vol. 40, No. 12, 1993, pp. 2245-2254.
12. R. Degraeve, B. Kaczer, A. De Keersgieter, G. Groeseneken, "Relation between breakdown mode and breakdown location in short channel NMOSFETS and its impact on reliability specifications", IRPS Proc. 2001, pp. 360-366.
13. B. P. Linder, J. H. Stathis, D. J. Frank, S. Lombardo and A. Vayshenker, "Growth and scaling of oxide conduction after breakdown", to be presented at the International Reliability Physics Symposium (IRPS2003).
14. E. Seevink, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid State Circuits, vol. SC-22, 1987, pp. 748-754.
15. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid State Circuits, vol. 36, 2001, pp. 658-665.
16. M. Hargrove, et al., "High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay," in IEDM Tech Dig., 1998, pp. 627-630.
17. J. Warnock et al., "The circuit and physical design of the POWER4 microprocessor," IBM J. Res. Dev. 2002, vol. 46, pp. 27-52.