Crosstalk fault modeling in defective pair of interconnects

Integration, the VLSI Journal

Volumn 41, Issue 1, 2008, Pages 27-37

  Palit, Ajoy K ^a   Duganapalli, Kishore K ^a   Anheier, Walter ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

ABCD model; Aggressor victim; Crosstalk hazards; Defect's severity; Line defect based crosstalk fault model; Signal integrity losses

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; FAULT TOLERANCE; FORMAL LOGIC; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; RELIABILITY THEORY; SPICE;

CROSSTALK HAZARDS; LINE-DEFECT-BASED CROSSTALK FAULT MODELS; SIGNAL INTEGRITY LOSSES;

OPTICAL INTERCONNECTS;

EID: 34548476457     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2007.04.005     Document Type: Article

References (7)

1. D. Arumi, R. Rodriguez-Montanes, J. Figueras, Defective behaviors of resistive opens in interconnect line, in: Proceedings of IEEE-ETS, Tallinn, Estonia, 22-25 May 2005, pp. 28-33.
2. Banerjee K., and Mehrotra A. Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Comp. Aided Des. Integr. Circuits Syst. 21 8 (2002) 904-915
3. G. Chen, S. Reddy, I. Pomeranz, J. Rajaski, P. Engelke, B. Becker, An unified fault model and test generation procedure for interconnect opens and bridges, in: Proceedings of IEEE-ETS 2005, Tallinn, Estonia, 22-25 May, pp. 22-27.
4. M. Cuviello, S. Dey, X. Bai, Y. Zhao, Fault modeling and simulation for crosstalk in system-on-chip interconnects, in: Proceedings of ICCAD 1999, San Jose, CA, USA, 7-11 November, pp. 297-303.
5. A.K. Palit, W. Anheier, J. Schloeffel, Estimation of signal integrity loss through reduced order interconnect model, in: Proceedings IEEE-SPI 2003, Siena, Italy, pp. 163-166.
6. A.K. Palit, L. Wu, K.K. Duganapalli, W. Anheier, J. Schloeffel, A new, flexible and very accurate crosstalk fault model to analyze the effects of coupling noise between the interconnects on signal integrity losses in deep submicron chips, paper no. 253, in: Proceedings of 14th IEEE-ATS'05, Calcutta, India, 18-21 December, pp. 22-26.
7. B. Young, Digital Signal Integrity: Modeling and Simulations with Interconnects and Packages, Prentice-Hall PTR, Upper Saddle River, NJ, 2001, pp. 98-101.