A fault-aware dynamic routing algorithm for on-chip networks

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 2653-2656

  Hosseini, Amir ^a   Ragheb, Tamer ^a   Massoud, Yehia ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARTS COMPUTING; BOOLEAN FUNCTIONS; ELECTRIC LOAD FORECASTING; ELECTRIC NETWORK TOPOLOGY; ERROR ANALYSIS; ERROR CORRECTION; ERRORS; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; NETWORK ROUTING; TECHNICAL PRESENTATIONS;

DYNAMIC ROUTING ALGORITHMS; ENERGY CONSUMPTION;

ROUTING ALGORITHMS;

EID: 51749123102     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4542002     Document Type: Conference Paper

References (12)

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