Modeling of interconnect capacitance, delay, and crosstalk in VLSI

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 1, 2000, Pages 108-111

  Wong, Shyh Chyi ^a   Lee, Gwo Yann ^b   Ma, Dye Jyun ^c  

^a WINBOND ELECTRONICS CORPORATION   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CROSSTALK; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS;

INTERCONNECT CAPACITANCE;

VLSI CIRCUITS;

EID: 0033873392     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.827350     Document Type: Article

References (8)

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