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Volumn , Issue , 2010, Pages 497-508

Relax: An architectural framework for software recovery of hardware faults

Author keywords

[No Author keywords available]

Indexed keywords

AMOUNT OF INFORMATION; ARCHITECTURAL FRAMEWORKS; CHECK POINTING; CORE COMPONENTS; EMERGING APPLICATIONS; ENERGY EFFICIENCY IMPROVEMENTS; FAULT RECOVERY; HARDWARE DESIGN; HARDWARE FAULTS; MANY-CORE ARCHITECTURE; PROCESS VARIATION; SIDE EFFECT; SOFTWARE RECOVERY; SOFTWARE SUPPORT; SOURCE CODE CHANGES; SUB-COMPUTATIONS; TECHNOLOGY SCALING;

EID: 77954968857     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1816026     Document Type: Conference Paper
Times cited : (162)

References (42)
  • 2
    • 84944413215 scopus 로고    scopus 로고
    • LLVA: A low-level virtual instruction set architecture
    • V. Adve, C. Lattner, M. Brukman, A. Shukla, and B. Gaeke. LLVA: A low-level virtual instruction set architecture. In MICRO '03, pages 205-216.
    • MICRO , vol.3 , pp. 205-216
    • Adve, V.1    Lattner, C.2    Brukman, M.3    Shukla, A.4    Gaeke, B.5
  • 3
    • 84944392430 scopus 로고    scopus 로고
    • Checkpoint processing and recovery: Towards scalable large instruction window processors
    • H. Akkary, R. Rajwar, and S. Srinivasan. Checkpoint processing and recovery: Towards scalable large instruction window processors. In MICRO '03, pages 423-434.
    • MICRO , vol.3 , pp. 423-434
    • Akkary, H.1    Rajwar, R.2    Srinivasan, S.3
  • 5
    • 24644506256 scopus 로고    scopus 로고
    • CodeSurfer/x86-A platform for analyzing x86 executables
    • Compiler Construction - 14th International Conference, CC 2005, held as part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Proceedings
    • G. Balakrishnan, R. Gruian, T. W. Reps, and T. Teitelbaum. Codesurfer/x86-a platform for analyzing x86 executables. In R. Bodík, editor, CC, volume 3443 of Lecture Notes in Computer Science, pages 250-254. Springer, 2005. (Pubitemid 41273910)
    • (2005) Lecture Notes in Computer Science , vol.3443 , pp. 250-254
    • Balakrishnan, G.1    Gruian, R.2    Reps, T.3    Teitelbaum, T.4
  • 7
    • 63549095070 scopus 로고    scopus 로고
    • The PARSEC benchmark suite: Characterization and architectural implications
    • C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In PACT '08, pages 72-81.
    • PACT , vol.8 , pp. 72-81
    • Bienia, C.1    Kumar, S.2    Singh, J.P.3    Li, K.4
  • 8
    • 33750415121 scopus 로고    scopus 로고
    • Automatic instruction-level software-only recovery
    • J. Chang, G. A. Reis, and D. I. August. Automatic instruction-level software-only recovery. In DSN '06, pages 83-92.
    • DSN , vol.6 , pp. 83-92
    • Chang, J.1    Reis, G.A.2    August, D.I.3
  • 9
    • 77954967124 scopus 로고    scopus 로고
    • A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism
    • M. de Kruijf, S. Nomura, and K. Sankaralingam. A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism. In DSN '10.
    • DSN , vol.10
    • De Kruijf, M.1    Nomura, S.2    Sankaralingam, K.3
  • 11
    • 79959860111 scopus 로고    scopus 로고
    • Exploring the synergy of emerging workloads and silicon reliability trends
    • M. de Kruijf and K. Sankaralingam. Exploring the synergy of emerging workloads and silicon reliability trends. In SELSE '09.
    • SELSE , vol.9
    • De Kruijf, M.1    Sankaralingam, K.2
  • 14
    • 47849119741 scopus 로고    scopus 로고
    • Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking
    • B. Greskamp and J. Torrellas. Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking. In PACT '07, pages 213-224.
    • PACT , vol.7 , pp. 213-224
    • Greskamp, B.1    Torrellas, J.2
  • 15
    • 64949118635 scopus 로고    scopus 로고
    • Blueshift: Designing processors for timing speculation from the ground up
    • B. Greskamp, L. Wan, U. Karpuzcu, J. Cook, J. Torrellas, D. Chen, and C. Zilles. Blueshift: Designing processors for timing speculation from the ground up. In HPCA '09, pages 213-224.
    • HPCA , vol.9 , pp. 213-224
    • Greskamp, B.1    Wan, L.2    Karpuzcu, U.3    Cook, J.4    Torrellas, J.5    Chen, D.6    Zilles, C.7
  • 17
    • 77954966863 scopus 로고    scopus 로고
    • System level analysis of fast, per-core DVFS using on-chip switching regulators
    • W. Kim, M. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. In HPCA '08, pages 213-224.
    • HPCA , vol.8 , pp. 213-224
    • Kim, W.1    Gupta, M.2    Wei, G.-Y.3    Brooks, D.4
  • 19
    • 35348855586 scopus 로고    scopus 로고
    • Carbon: Architectural support for fine-grained parallelism on chip multiprocessors
    • S. Kumar, C. J. Hughes, and A. Nguyen. Carbon: architectural support for fine-grained parallelism on chip multiprocessors. In ISCA '07, pages 162-173.
    • ISCA , vol.7 , pp. 162-173
    • Kumar, S.1    Hughes, C.J.2    Nguyen, A.3
  • 20
    • 3042658703 scopus 로고    scopus 로고
    • LLVM: A compilation framework for lifelong program analysis & transformation
    • C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO '04, pages 75-88.
    • CGO , vol.4 , pp. 75-88
    • Lattner, C.1    Adve, V.2
  • 21
    • 77957781457 scopus 로고    scopus 로고
    • Understanding the propagation of hard errors to software and implications for resilient system design
    • M. Li, P. Ramachandran, S. K. Sahoo, S. V. Adve, V. S. Adve, and Y. Zhou. Understanding the propagation of hard errors to software and implications for resilient system design. In ASPLOS '08, pages 265-276.
    • ASPLOS , vol.8 , pp. 265-276
    • Li, M.1    Ramachandran, P.2    Sahoo, S.K.3    Adve, S.V.4    Adve, V.S.5    Zhou, Y.6
  • 22
    • 34547697289 scopus 로고    scopus 로고
    • Application-level correctness and its impact on fault tolerance
    • X. Li and D. Yeung. Application-level correctness and its impact on fault tolerance. In HPCA '07, pages 181-192.
    • HPCA , vol.7 , pp. 181-192
    • Li, X.1    Yeung, D.2
  • 25
    • 41349107838 scopus 로고    scopus 로고
    • Argus: Low-cost comprehensive error detection in simple cores
    • A. Meixner, M. E. Bauer, and D. J. Sorin. Argus: Low-cost comprehensive error detection in simple cores. IEEE Micro, 28(1):52-59, 2008.
    • (2008) IEEE Micro , vol.28 , Issue.1 , pp. 52-59
    • Meixner, A.1    Bauer, M.E.2    Sorin, D.J.3
  • 26
    • 47349119719 scopus 로고    scopus 로고
    • Effective optimistic-checker tandem core design through architectural pruning
    • F. Mesa-Martinez and J. Renau. Effective optimistic-checker tandem core design through architectural pruning. In MICRO '07, pages 236-248.
    • MICRO , vol.7 , pp. 236-248
    • Mesa-Martinez, F.1    Renau, J.2
  • 27
    • 0036287327 scopus 로고    scopus 로고
    • Detailed design and evaluation of redundant multi-threading alternatives
    • S. Mukherjee, M. Kontz, and S. Reinhardt. Detailed design and evaluation of redundant multi-threading alternatives. In ISCA '02, pages 99-110.
    • ISCA , vol.2 , pp. 99-110
    • Mukherjee, S.1    Kontz, M.2    Reinhardt, S.3
  • 28
    • 84955506994 scopus 로고    scopus 로고
    • Runahead execution: An alternative to very large instruction windows for out-of-order processors
    • O. Mutlu, J. Stark, C. Wilkerson, and Y. Patt. Runahead execution: an alternative to very large instruction windows for out-of-order processors. In HPCA '03, pages 129-140.
    • HPCA , vol.3 , pp. 129-140
    • Mutlu, O.1    Stark, J.2    Wilkerson, C.3    Patt, Y.4
  • 31
    • 70450271056 scopus 로고    scopus 로고
    • Architectural core salvaging in a multi-core processor for hard-error tolerance
    • M. D. Powell, A. Biswas, S. Gupta, and S. S. Mukherjee. Architectural core salvaging in a multi-core processor for hard-error tolerance. In ISCA '09, pages 93-104.
    • ISCA , vol.9 , pp. 93-104
    • Powell, M.D.1    Biswas, A.2    Gupta, S.3    Mukherjee, S.S.4
  • 32
    • 0036290620 scopus 로고    scopus 로고
    • ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors
    • M. Prvulovic, Z. Zhang, and J. Torrellas. ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors. In ISCA '02, pages 111-122.
    • ISCA , vol.2 , pp. 111-122
    • Prvulovic, M.1    Zhang, Z.2    Torrellas, J.3
  • 34
    • 53349128424 scopus 로고    scopus 로고
    • Using likely program invariants to detect hardware errors
    • S. Sahoo, M.-L. Li, P. Ramachandran, S. Adve, V. Adve, and Y. Zhou. Using likely program invariants to detect hardware errors. In DSN '08, pages 70-79, 2008.
    • (2008) DSN , vol.8 , pp. 70-79
    • Sahoo, S.1    Li, M.-L.2    Ramachandran, P.3    Adve, S.4    Adve, V.5    Zhou, Y.6
  • 36
    • 40349114890 scopus 로고    scopus 로고
    • Reunion: Complexity-effective multicore redundancy
    • J. C. Smolens, B. T. Gold, B. Falsafi, and J. C. Hoe. Reunion: Complexity-effective multicore redundancy. In MICRO '06, pages 223-234.
    • MICRO , vol.6 , pp. 223-234
    • Smolens, J.C.1    Gold, B.T.2    Falsafi, B.3    Hoe, J.C.4
  • 37
    • 77956574682 scopus 로고    scopus 로고
    • Fault tolerant computer architecture
    • D. J. Sorin. Fault Tolerant Computer Architecture. Morgan & Claypool, 2009.
    • (2009) Morgan & Claypool
    • Sorin, D.J.1
  • 38
    • 0036292677 scopus 로고    scopus 로고
    • SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery
    • D. J. Sorin, M. M. K. Martin, M. D. Hill, and D. A. Wood. SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery. In ISCA '02, pages 123-134.
    • ISCA , vol.2 , pp. 123-134
    • Sorin, D.J.1    Martin, M.M.K.2    Hill, M.D.3    Wood, D.A.4
  • 40
    • 0036858210 scopus 로고    scopus 로고
    • Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
    • DOI 10.1109/JSSC.2002.803949
    • J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE Journal of Solid-State Circuits, 37(11):1396-1402, 2002. (Pubitemid 35432159)
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , Issue.11 , pp. 1396-1402
    • Tschanz, J.W.1    Kao, J.T.2    Narendra, S.G.3    Nair, R.4    Antoniadis, D.A.5    Chandrakasan, A.P.6    De, V.7
  • 42
    • 84859074837 scopus 로고    scopus 로고
    • Soft error resilience of probabilistic inference applications
    • V. Wong and M. Horowitz. Soft error resilience of probabilistic inference applications. In SELSE '06.
    • SELSE , vol.6
    • Wong, V.1    Horowitz, M.2


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