-
1
-
-
42649120679
-
Ray Tracing on the CELL Processor
-
C. Benthin, I. Wald, M. Scherbaum, and H. Friedrich, "Ray Tracing on the CELL Processor," in Interactive Ray Tracing, 2006, pp. 15-23.
-
(2006)
Interactive Ray Tracing
, pp. 15-23
-
-
Benthin, C.1
Wald, I.2
Scherbaum, M.3
Friedrich, H.4
-
2
-
-
42549098900
-
Design for parallel interactive ray tracing systems
-
J. Bigler, A. Stephens, and S. Parker, "Design for parallel interactive ray tracing systems," in Interactive Ray Tracing, 2006, pp. 187-196.
-
(2006)
Interactive Ray Tracing
, pp. 187-196
-
-
Bigler, J.1
Stephens, A.2
Parker, S.3
-
3
-
-
0346898058
-
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
-
D. Brooks, P. Bose, V. Srinivasan, M. K. Gschwind, P. G. Emma, and M. G. Rosenfleld, "New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors," IBM J. Res. Dev., vol. 47, no. 5-6, pp. 653-670, 2003.
-
(2003)
IBM J. Res. Dev
, vol.47
, Issue.5-6
, pp. 653-670
-
-
Brooks, D.1
Bose, P.2
Srinivasan, V.3
Gschwind, M.K.4
Emma, P.G.5
Rosenfleld, M.G.6
-
4
-
-
34547678136
-
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping
-
N. Clark, A. Hormati, S. Yehia, S. Mahlke, and K. Flaut-ner, "Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping," in HPCA '07, pp. 216-227.
-
HPCA '07
, pp. 216-227
-
-
Clark, N.1
Hormati, A.2
Yehia, S.3
Mahlke, S.4
Flaut-ner, K.5
-
5
-
-
80155142239
-
Razor: An architecture for dynamic multiresolution ray tracing
-
P. Djeu, W. Hunt, R. Wang, I. Elhassan, G. Stoll, and W. R. Mark, "Razor: An architecture for dynamic multiresolution ray tracing," Conditionally accepted to ACM Transactions on Graphics (available as UT Austin CS Tech Report TR-07-52).
-
Conditionally accepted to ACM Transactions on Graphics (available as UT Austin CS Tech Report TR-07-52)
-
-
Djeu, P.1
Hunt, W.2
Wang, R.3
Elhassan, I.4
Stoll, G.5
Mark, W.R.6
-
6
-
-
0242577987
-
Statistical simulation: Adding efficiency to the computer designer's toolbox
-
L. Eeckhout, S. Nussbaum, J. E. Smith, and K. D. Bosschere, "Statistical simulation: Adding efficiency to the computer designer's toolbox," IEEE Micro, vol. 23, no. 5, pp. 26-38, 2003.
-
(2003)
IEEE Micro
, vol.23
, Issue.5
, pp. 26-38
-
-
Eeckhout, L.1
Nussbaum, S.2
Smith, J.E.3
Bosschere, K.D.4
-
8
-
-
0036296817
-
The optimum pipeline depth for a microprocessor
-
A. Hartstein and T. R. Puzak, "The optimum pipeline depth for a microprocessor," in ISCA '02, pp. 7-13.
-
ISCA '02
, pp. 7-13
-
-
Hartstein, A.1
Puzak, T.R.2
-
9
-
-
49249134204
-
Interactive k-d tree gpu raytracing
-
D. R. Horn, J. Sugerman, M. Houston, and P. Hanrahan, "Interactive k-d tree gpu raytracing," in I3D '07, pp. 167-174.
-
I3D '07
, pp. 167-174
-
-
Horn, D.R.1
Sugerman, J.2
Houston, M.3
Hanrahan, P.4
-
10
-
-
35348826095
-
Physical simulation for animation and visual effects: Parallelization and characterization for chip multiprocessors
-
C. J. Hughes, R. Grzeszczuk, E. Sifakis, D. Kim, S. Kumar, A. P. Selle, J. Chhugani, M. Holliman, and Y.-K. Chen, "Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors," in ISCA '07, pp. 220-231.
-
ISCA '07
, pp. 220-231
-
-
Hughes, C.J.1
Grzeszczuk, R.2
Sifakis, E.3
Kim, D.4
Kumar, S.5
Selle, A.P.6
Chhugani, J.7
Holliman, M.8
Chen, Y.-K.9
-
11
-
-
66749097272
-
Efficient architectural design space exploration via predictive modeling
-
E. Ipek, S. A. McKee, K. Singh, R. Caruana, B. R. de Supinski, and M. Schulz, "Efficient architectural design space exploration via predictive modeling," ACM Trans. Archit. Code Optim., vol. 4, no. 4, pp. 1-34, 2008.
-
(2008)
ACM Trans. Archit. Code Optim
, vol.4
, Issue.4
, pp. 1-34
-
-
Ipek, E.1
McKee, S.A.2
Singh, K.3
Caruana, R.4
de Supinski, B.R.5
Schulz, M.6
-
12
-
-
35348870650
-
Automated design of application specific superscalar processors: An analytical approach
-
T. Karkhanis and J. E. Smith, "Automated design of application specific superscalar processors: an analytical approach," in ISCA '07, pp. 402-411.
-
ISCA '07
, pp. 402-411
-
-
Karkhanis, T.1
Smith, J.E.2
-
13
-
-
4644299010
-
A first-order superscalar processor model
-
T. Karkhanis, "A first-order superscalar processor model," in ISCA '04, pp. 338-349.
-
ISCA '04
, pp. 338-349
-
-
Karkhanis, T.1
-
14
-
-
35348855586
-
Carbon: Architectural support for fine-grained parallelism on chip multiprocessors
-
S. Kumar, C. J. Hughes, and A. Nguyen, "Carbon: architectural support for fine-grained parallelism on chip multiprocessors," in ISCA '07, pp. 162-173.
-
ISCA '07
, pp. 162-173
-
-
Kumar, S.1
Hughes, C.J.2
Nguyen, A.3
-
16
-
-
34547288276
-
Accurate and efficient regression modeling for microarchitectural performance and power prediction
-
B. C. Lee and D. M. Brooks, "Accurate and efficient regression modeling for microarchitectural performance and power prediction," in ASPLOS-XII, pp. 185-194.
-
ASPLOS-XII
, pp. 185-194
-
-
Lee, B.C.1
Brooks, D.M.2
-
17
-
-
52649125840
-
3D-Stacked Memory Architectures for Multi-core Processors
-
G. H. Loh, "3D-Stacked Memory Architectures for Multi-core Processors," in ISCA '08, pp. 453-464.
-
ISCA '08
, pp. 453-464
-
-
Loh, G.H.1
-
18
-
-
33748870886
-
Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset
-
M. M. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood, "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News (CAN), 2005.
-
(2005)
Computer Architecture News (CAN)
-
-
Martin, M.M.1
Sorin, D.J.2
Beckmann, B.M.3
Marty, M.R.4
Xu, M.5
Alameldeen, A.R.6
Moore, K.E.7
Hill, M.D.8
Wood, D.A.9
-
19
-
-
25844485467
-
Characterization of simultaneous multithreading (smt) efficiency in power5
-
H. M. Mathis, A. E. Mericas, J. D. McCalpin, R. J. Eickemeyer, and S. R. Kunkel, "Characterization of simultaneous multithreading (smt) efficiency in power5," IBM Journal of Research and Development, vol. 49, no. 4-5, pp. 555-564, 2005.
-
(2005)
IBM Journal of Research and Development
, vol.49
, Issue.4-5
, pp. 555-564
-
-
Mathis, H.M.1
Mericas, A.E.2
McCalpin, J.D.3
Eickemeyer, R.J.4
Kunkel, S.R.5
-
20
-
-
84945128980
-
PAPI Deployment, Evaluation, and Extensions
-
S. Moore, D. Terpstra, K. London, P. Mucci, P. Teller, L. Salayandia, A. Bayona, and M. Nieto, "PAPI Deployment, Evaluation, and Extensions," in DOD-UGC '03, pp. 349-353.
-
DOD-UGC '03
, pp. 349-353
-
-
Moore, S.1
Terpstra, D.2
London, K.3
Mucci, P.4
Teller, P.5
Salayandia, L.6
Bayona, A.7
Nieto, M.8
-
22
-
-
85016676932
-
Theoretical modeling of superscalar processor performance
-
D. B. Noonburg and J. P. Shen, "Theoretical modeling of superscalar processor performance," in MICRO '94, pp. 52-62.
-
MICRO '94
, pp. 52-62
-
-
Noonburg, D.B.1
Shen, J.P.2
-
23
-
-
84856504643
-
Interactive ray tracing
-
S. Parker, W. Martin, P.-P. J. Sloan, P. Shirley, B. Smits, and C. Hansen, "Interactive ray tracing," in SIGGRAPH '05 Courses.
-
SIGGRAPH '05 Courses
-
-
Parker, S.1
Martin, W.2
Sloan, P.-P.J.3
Shirley, P.4
Smits, B.5
Hansen, C.6
-
24
-
-
33748872867
-
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
-
D. Penry, D. Fay, D. Hodgdon, R. Wells, G. Schelle, D. August, and D. Connors, "Exploiting parallelism and structure to accelerate the simulation of chip multi-processors," in HPCA '06, pp. 29-40.
-
HPCA '06
, pp. 29-40
-
-
Penry, D.1
Fay, D.2
Hodgdon, D.3
Wells, R.4
Schelle, G.5
August, D.6
Connors, D.7
-
26
-
-
66749091672
-
-
Pin: http://rogue.colorado.edu/wikipin/index.php/downloads.
-
"Pin: http://rogue.colorado.edu/wikipin/index.php/downloads."
-
-
-
-
27
-
-
36348941824
-
Pipeline spectroscopy
-
T. R. Puzak, A. Hartstein, V. Srinivasan, P. G. Emma, and A. Nadas, "Pipeline spectroscopy," in SIGMETRICS '07, pp. 351-352.
-
SIGMETRICS '07
, pp. 351-352
-
-
Puzak, T.R.1
Hartstein, A.2
Srinivasan, V.3
Emma, P.G.4
Nadas, A.5
-
28
-
-
0003078124
-
Dynamic acceleration structures for interactive ray tracing
-
E. Reinhard, B. E. Smits, and C. Hansen, "Dynamic acceleration structures for interactive ray tracing," in Eurographics Workshop on Rendering Techniques, 2000, pp. 299-306.
-
(2000)
Eurographics Workshop on Rendering Techniques
, pp. 299-306
-
-
Reinhard, E.1
Smits, B.E.2
Hansen, C.3
-
29
-
-
84944402628
-
Universal Mechanisms for Data-Parallel Architectures
-
K. Sankaralingam, S. W. Keckler, W. R. Mark, and D. Burger, "Universal Mechanisms for Data-Parallel Architectures," in MICRO '03, pp. 303-314.
-
MICRO '03
, pp. 303-314
-
-
Sankaralingam, K.1
Keckler, S.W.2
Mark, W.R.3
Burger, D.4
-
30
-
-
49249086142
-
Larrabee: A many-core x86 architecture for visual computing
-
L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan, "Larrabee: a many-core x86 architecture for visual computing," in SIGGRAPH '08, 2008, pp. 1-15.
-
(2008)
SIGGRAPH '08
, pp. 1-15
-
-
Seiler, L.1
Carmean, D.2
Sprangle, E.3
Forsyth, T.4
Abrash, M.5
Dubey, P.6
Junkins, S.7
Lake, A.8
Sugerman, J.9
Cavin, R.10
Espasa, R.11
Grochowski, E.12
Juan, T.13
Hanrahan, P.14
-
31
-
-
0003438155
-
Efficiency issues for ray tracing
-
B. Smits, "Efficiency issues for ray tracing," J. Graph. Tools, vol. 3, no. 2, pp. 1-14, 1998.
-
(1998)
J. Graph. Tools
, vol.3
, Issue.2
, pp. 1-14
-
-
Smits, B.1
-
32
-
-
0031593993
-
analytic evaluation of sharedmemory parallel systems with ilp processors
-
D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood, "analytic evaluation of sharedmemory parallel systems with ilp processors"," in Proc. 25th Int'l. Symp. on Computer Architecture (ISCA '98), 1998, pp. 380-391.
-
(1998)
Proc. 25th Int'l. Symp. on Computer Architecture (ISCA '98)
, pp. 380-391
-
-
Sorin, D.J.1
Pai, V.S.2
Adve, S.V.3
Vernon, M.K.4
Wood, D.A.5
-
33
-
-
52349084097
-
Trax: A multi-threaded architecture for real-time ray tracing
-
J. Spjut, S. Boulos, D. Kopta, E. Brunvand, and S. Kellis, "Trax: A multi-threaded architecture for real-time ray tracing," in SASP '08, pp. 108-114.
-
SASP '08
, pp. 108-114
-
-
Spjut, J.1
Boulos, S.2
Kopta, D.3
Brunvand, E.4
Kellis, S.5
-
34
-
-
84948974161
-
Optimizing pipelines for power and performance
-
V. Srinivasan, D. Brooks, M. Gschwind, P. Bose, V. V. Zyuban, P. N. Strenski, and P. G. Emma, "Optimizing pipelines for power and performance," in MICRO '02, pp. 333-344.
-
MICRO '02
, pp. 333-344
-
-
Srinivasan, V.1
Brooks, D.2
Gschwind, M.3
Bose, P.4
Zyuban, V.V.5
Strenski, P.N.6
Emma, P.G.7
-
35
-
-
42549160830
-
Estimating performance of a ray-tracing asic design
-
September
-
E. B. Sven Woop and P. Slusallek, "Estimating performance of a ray-tracing asic design," in Interactive Ray Tracing, September 2006, pp. 7-14.
-
(2006)
Interactive Ray Tracing
, pp. 7-14
-
-
Sven Woop, E.B.1
Slusallek, P.2
-
36
-
-
30744459395
-
RPU: A Programmable Ray Processing Unit for Realtime Ray Tracing
-
J. S. Sven Woop and P. Slusallek, "RPU: A Programmable Ray Processing Unit for Realtime Ray Tracing," in SIGGRAPH '05, pp. 434 - 444.
-
SIGGRAPH '05
, pp. 434-444
-
-
Sven Woop, J.S.1
Slusallek, P.2
-
38
-
-
66749086980
-
Distributed interactive ray tracing of dynamic scenes
-
I. Wald, C. Benthin, and P. Slusallek, "Distributed interactive ray tracing of dynamic scenes," in PVG '03, p. 11.
-
PVG '03
, pp. 11
-
-
Wald, I.1
Benthin, C.2
Slusallek, P.3
-
39
-
-
0842274749
-
Realtime Ray Tracing and its use for Interactive Global Illumination,
-
I. Wald, T. J. Purcell, J. Schmittler, C. Benthin, and P. Slusallek, "Realtime Ray Tracing and its use for Interactive Global Illumination," in Eurographics State of the Art Reports, 2003.
-
(2003)
Eurographics State of the Art Reports
-
-
Wald, I.1
Purcell, T.J.2
Schmittler, J.3
Benthin, C.4
Slusallek, P.5
-
40
-
-
36948999360
-
B-KD Trees for Hardware Accelerated Ray Tracing of Dynamic Scenes
-
S. Woop, G. Marmitt, and P. Slusallek, "B-KD Trees for Hardware Accelerated Ray Tracing of Dynamic Scenes," in Proceedings of Graphics Hardware, 2006, pp. 67-77.
-
(2006)
Proceedings of Graphics Hardware
, pp. 67-77
-
-
Woop, S.1
Marmitt, G.2
Slusallek, P.3
-
41
-
-
35348820508
-
A 64-bit stream processor architecture for scientific applications
-
X. Yang, X. Yan, Z. Xing, Y. Deng, J. Jiang, and Y. Zhang, "A 64-bit stream processor architecture for scientific applications," in ISCA '07, pp. 210-219.
-
ISCA '07
, pp. 210-219
-
-
Yang, X.1
Yan, X.2
Xing, Z.3
Deng, Y.4
Jiang, J.5
Zhang, Y.6
-
42
-
-
35348814920
-
Parallax: An architecture for real-time physics
-
T. Y Yeh, P. Faloutsos, S. J. Patel, and G. Reinman, "Parallax: an architecture for real-time physics," in ISCA '07, pp. 232-243.
-
ISCA '07
, pp. 232-243
-
-
Yeh, T.Y.1
Faloutsos, P.2
Patel, S.J.3
Reinman, G.4
-
43
-
-
3242680845
-
Integrated analysis of power and performance for pipelined microprocessors
-
V. V. Zyuban, D. Brooks, V. Srinivasan, M. Gschwind, P. Bose, P. N. Strenski, and P. G. Emma, "Integrated analysis of power and performance for pipelined microprocessors," IEEE Trans. Computers, vol. 53, no. 8, pp. 1004-1016, 2004.
-
(2004)
IEEE Trans. Computers
, vol.53
, Issue.8
, pp. 1004-1016
-
-
Zyuban, V.V.1
Brooks, D.2
Srinivasan, V.3
Gschwind, M.4
Bose, P.5
Strenski, P.N.6
Emma, P.G.7
|