Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2007, Pages 213-224

  Greskamp, Brian ^a   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; ERROR CORRECTION; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; TURBO CODES;

CHIP MULTI PROCESSOR; COMPILATION TECHNIQUES; GEOMETRIC MEAN; HARDWARE DESIGNS; INTERNATIONAL CONFERENCES; MICRO ARCHITECTURES; NANO SCALING; OVERCLOCKING; PARALLEL ARCHITECTURES; POWER DENSITIES; PREFETCHES; SINGLE-THREAD PERFORMANCE; SOFT ERRORS; TRANSIENT FAULTS; WORST-CASE DESIGN;

PARALLEL PROCESSING SYSTEMS;

EID: 47849119741     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2007.4336213     Document Type: Conference Paper

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