3D system integration technologies

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2006, Pages 19-27

  Beyne, Eric ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRONICS PACKAGING; MULTILAYERS; PASSIVATION; SILICON WAFERS;

VERTICAL CONNECTIONS;

INTEGRATED CIRCUIT LAYOUT;

EID: 34249801921     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2006.251113     Document Type: Conference Paper

References (16)

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12. Misma Koyanagi, "3D LSI Technology and Wafer-level Stack", idem [7], pp.101-108.
13. E.Beyne, "Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits", IEEE-IEDM 2001 Technical Digest, December 2-5, Washington, D.C., S23-p3, 2001.
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15. patent US 10817763
16. patent EP 0100014, US 6,506,664