High-performance vertical interconnection for high-density 3D chip stacking package

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 616-623

  Umemoto, Mitsuo ^a   Tanida, Kazumasa ^a   Nemoto, Yoshihiko ^a   Hoshino, Masataka ^a   Kojima, Kazumi ^a   Shirai, Yuji ^a   Takahashi, Kenji ^a  

^a Assoc Super Adv Electronics T   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFUSION; INTERCONNECTION NETWORKS; INVESTMENTS; RELIABILITY; SCANNING ELECTRON MICROSCOPY; SIGNAL THEORY;

CHIP STACKING PACKAGE; MICRO SCALE STRIP LINE; SYSTEM INTEGRATION; VERTICAL INTERCONNECTION;

CHIP SCALE PACKAGES;

EID: 10444270123     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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