Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 943-945

  Guarini, K W ^a   Topol, A W ^a   Ieong, M ^b   Yu, R ^b   Shi, L ^a   Newport, M R ^b   Frank, D J ^a   Singh, D V ^a   Cohen, G M ^a   Nitta, S V ^a   Boyd, D C ^b   O'Neil, P A ^b   Tempest, S L ^b   Pogge, H B ^b   Purushothaman, S ^a   Haensch, W E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY; FABRICATION; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THRESHOLD VOLTAGE;

THREE-DIMENSIONAL INTEGRATED CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0036928172     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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