Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 853-858

  Kuo, Tzu Ying ^a   Chang, Shu Ming ^a   Shih, Ying Ching ^a   Chiang, Chia Wen ^a   Hsu, Chao Kai ^a   Lee, Ching Kuan ^a   Lin, Chun Te ^a   Chen, Yu Hua ^a   Lo, Wei Chung ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; INTEGRATED CIRCUIT MANUFACTURE; LASERS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; PRINTED CIRCUITS; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; TECHNOLOGY; TESTING; THREE DIMENSIONAL; WAFER BONDING;

FORMING PROCESSES; LOW COSTS; TESTING RESULTS;

ELECTRONICS PACKAGING;

EID: 51349096634     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550076     Document Type: Conference Paper

References (9)

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