Development and characterization of low cost ultrathin 3D interconnect

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 337-342

  Lo, Wei Chung ^a   Chen, Yu Hua ^a   Ko, Jeng Dar ^a   Kuo, Tzu Ying ^a   Chien, Chien Wei ^a   Chen, Yu Chih ^a   Chen, Wun Yan ^a   Leu, Fang Jun ^a   Hu, Hsu Tien ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION; ELECTRONICS PACKAGING; ELECTROPLATING; RELIABILITY; SILICON; THREE DIMENSIONAL;

ELECTRICAL ISOLATION; ELECTROPLATING TECHNOLGY; THERMAL CYCLING TEST; VERTICAL INTERCONNECTIONS;

OPTICAL INTERCONNECTS;

EID: 24644507265     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. rd Electronic Components and Technology Conf, New Orleans, Louisiana, May. 2003, pp. 1147-1152.
4. K. Takahashi, et al., "Current Status of Research and Development for Three-Dimensional Chip Stack Technology," Jpn. J. Appl. Phys., Vol. 40, No.4 B(2001), pp.3032-3037.
5. L. Schaper, et al., "System Architecture Implications of 3D Interconnect Technologies," Proc. Int. Conf. On Advanced Packaging and Systems, pp.33-37
6. th Electronic Component and Technology Conference, 2004, pp.466-471
7. th Electronic Components and Technology Conf, 2004, pp. 616-623.
8. C. Chien, et al., "3D Chip Stack with Wafer Through Hole Technology", 10th SMTA : PanPacific microelectronics symposium, 2005,