3D chip-to-chip stacking with through silicon interconnects

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Lo, Wei Chung ^a   Chang, Shu Ming ^a   Chen, Yu Hua ^a   Ko, Jeng Dar ^a   Kuo, Tzu Ying ^a   Chang, Hsiang Hung ^a   Shih, Ying Ching ^a  

^a EOL/ITRI R000   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; SILICON COMPOUNDS; SILICON WAFERS; THERMAL EFFECTS; THREE DIMENSIONAL;

3D CHIP-TO-CHIP STACKING; LASER-DRILLED THROUGH SILICON INTERCONNECT(LTSI); WAFER STACKING;

OPTICAL INTERCONNECTS;

EID: 34548833875     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378925     Document Type: Conference Paper

References (6)

1. P. Ramm, et al., "Three dimensional metallization for vertically integrated circuits, " Microelectron. Eng., Vol. 3738 (1997), pp.39-47.
2. K. Takahashi, et al., "Current Status of Research and Development for Three-Dimensional Chip Stack Technology," Jpn. J. Appl. Phys., Vol. 40, No.4 B(2001), pp.3032-3037.
3. rd Electronic Components and Technology Conf, New Orleans, Louisiana, May, 2003, pp. 1147-1152.
4. th Electronic Components and Technology Conf., 2006, pp. 337-342.
5. th Electronic Component and Technology Conference, 2004, pp.466-471
6. th Electronic Components and Technology Conf., 2005, pp. 343-348.