Design of a feasible on-chip interconnection network for a Chip Multiprocessor (CMP)

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2007, Pages 211-218

  Lee, Seung Eun ^a   Bahn, Jun Ho ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ROUTERS; ADAPTIVE ROUTING ALGORITHMS; CHIP MULTI PROCESSOR (CMP); FEASIBLE DESIGN; FIXED PRIORITY (FP); HIGH PERFORMANCE COMPUTING (HIPC); INTERNATIONAL SYMPOSIUM; MESH TOPOLOGIES; MULTI PROCESSORS; ON CHIP INTERCONNECTION NETWORKS; OPTIMAL PERFORMANCES; OPTIMAL SIZE; SOC DESIGNS; WORMHOLE SWITCHING;

ADAPTIVE ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; INTERCONNECTION NETWORKS; MESH GENERATION; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; NETWORK ARCHITECTURE; NETWORK ROUTING; PACKET NETWORKS; ROUTERS; TELECOMMUNICATION NETWORKS;

ROUTING ALGORITHMS;

EID: 47249096169     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBAC-PAD.2007.18     Document Type: Conference Paper

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