Regional congestion awareness for load balance in networks-on-chip

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 203-214

  Gratz, Paul ^a   Grot, Boris ^b   Keckler, Stephen W ^b  

^a The University of Texas at Austin

^b University of Texas at Austin

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ROUTERS; ADAPTIVE ROUTING; ADAPTIVE ROUTING ALGORITHMS; BASE-LINES; BURSTY TRAFFICS; GLOBAL LOADS; GLOBAL NETWORKS; IMPLEMENTATION COMPLEXITIES; IN CHIPS; LATENCY REDUCTIONS; LOAD BALANCES; NETWORK THROUGHPUTS; NETWORKS ON CHIPS; NON UNIFORMS; ROUTING POLICIES; SYSTEM-ON-CHIP DESIGNS; TOLERANCE CHARACTERISTICS;

ADAPTIVE ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTERS; FAULT TOLERANCE; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; METROPOLITAN AREA NETWORKS; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; RELIABILITY; ROUTERS; TELECOMMUNICATION NETWORKS;

ROUTING ALGORITHMS;

EID: 57749191721     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658640     Document Type: Conference Paper

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