Larrabee: A many-core x86 architecture for visual computing

IEEE Micro

Volumn 29, Issue 1, 2009, Pages 10-21

  Seiler, Larry ^a   Carmean, Doug ^a   Sprangle, Eric ^a   Forsyth, Tom ^a   Dubey, Pradeep ^a   Junkins, Stephen ^a   Lake, Adam ^a   Cavin, Robert ^a   Espasa, Roger ^a   Grochowski, Ed ^a   Juan, Toni ^a   Abrash, Michael ^b   Sugarman, Jeremy ^c   Hanrahan, Pat ^c  

^a INTEL CORPORATION   (United States)

^b RAD Games Tools ^*

^c STANFORD UNIVERSITY   (United States)

Author keywords

Computer architecture; GPGPU; graphics architecture; Magnetic cores; many core computing; parallel processing; Pixel; real time graphics; Registers; Rendering (computer graphics); SIMD; Software; software rendering; throughput computing; Tiles; visual computing

Indexed keywords

ARCHITECTURE; BUILDING MATERIALS; COMPUTER GRAPHICS; COMPUTERS; MAGNETIC CIRCUITS; MAGNETIC CORES; MAGNETIC DEVICES; PIXELS; PROGRAM PROCESSORS;

GPGPU; GRAPHICS ARCHITECTURE; MANY-CORE COMPUTING; PARALLEL PROCESSING; REAL-TIME GRAPHICS; REGISTERS; RENDERING (COMPUTER GRAPHICS); SIMD; SOFTWARE; SOFTWARE RENDERING; THROUGHPUT COMPUTING; VISUAL COMPUTING;

COMPUTER ARCHITECTURE;

EID: 63149128672     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2009.9     Document Type: Conference Paper

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