Solder wetting in a wafer-level flip chip assembly

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 24, Issue 3, 2001, Pages 154-159

  Lu, Jicun ^a,b   Busch, Stephen C ^b   Baldwin, Daniel F ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Assembly; Flip chip; Solder wetting; Underfill; Wafer level

Indexed keywords

SOLDER WETTING; WAFER LEVELS;

HIGH SPEED CAMERAS; METALLIZING; REAL TIME SYSTEMS; SOLDERING; SURFACE MOUNT TECHNOLOGY; THERMODYNAMIC STABILITY; VISCOSITY; WETTING;

FLIP CHIP DEVICES;

EID: 0035401597     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/6104.956800     Document Type: Article

References (12)

1. The great underfill race
2. Wafer-level flip chip: Bumps flux underflip
3. Evaluation of fast-flow, fast-cure underfills for flip chip on organic substrate
4. Study on the pressurized underfill encapsulation of flip chips
5. High throughput flip chip processing and reliability analysis using no-flow underfills
6. High reliable and mass productionablef, flip chip package using non conductive film resin
7. Recent advance on a wafer-level flip chip packaging process
8. Coating and dicing of wafer applied underfills for low cost flip chip processing
9. Wafer scale packaging based on underfill applied at the wafer-level for low-cost flip chip processing
10. Manufacturing of Cu/electroless Nickel/Sn-Pb flip chip solder bumps
11. Study on the relationship between the surface composition of copper pads and no-flow underfill fluxing capability
12. A study on wettability and defects behaviour of flow-soldered joint using low residue flux