Instruction scheduling for VLIW processors under variation scenario

Proceedings - 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009

Volumn , Issue , 2009, Pages 33-40

  Mujadiya, Nayan V ^a  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPILE TIME; FUNCTIONAL UNITS; INSTRUCTION SCHEDULING; LEAKAGE ENERGIES; NONUNIFORM; ON-DEMAND; PERFORMANCE PENALTIES; PROCESS VARIATION; VLIW PROCESSOR;

EMBEDDED SYSTEMS; ENERGY DISSIPATION; TURNING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

COMPUTER SIMULATION;

EID: 71949101278     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2009.5289239     Document Type: Conference Paper

References (32)

1. S. Nassif, "Within-chip variability analysis," Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International, pp. 283-286, Dec 1998.
2. -, "Modeling and analysis of manufacturing variations," Custom Integrated Circuits, 2001, IEEE Conference on., pp. 223-228, 2001.
3. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in DAC '03: Proceedings of the 40th conference on Design automation. New York, NY, USA: ACM, 2003, pp. 338-342.
4. K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and withindie parameter fluctuations on the maximum clock frequency distribution for gigascale integration," Solid-State Circuits, IEEE Journal of, vol. 37, no. 2, pp. 183-190, Feb 2002.
5. P. S. Zuchowski, P. A. Habitz, J. D. Hayes, and J. H. Oppold, "Process and environmental variation impacts on asic timing," in ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computeraided design. Washington, DC, USA: IEEE Computer Society, 2004, pp. 336-342.
6. H. S. Kim, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Adapting instruction level parallelism for optimizing leakage in vliw architectures," SIGPLAN Not., vol. 38, no. 7, pp. 275-283, 2003.
7. L. N. Chakrapani, J. Gyllenhaal, W. mei W. Hwu, S. A. Mahlke, K. V. Palem, and R. M. Rabbah, "Trimaran: An infrastructure for research in instruction-level parallelism," in Lecture Notes in Computer Science, 2004, p. 2005.
8. Y.-F. Tsai, A. Ankadi, N. Vijaykrishnan, M. Irwin, and T. Theocharides, "Chippower: an architecture-level leakage simulator," SOC Conference, 2004. Proceedings. IEEE International, pp. 395-398, Sept. 2004.
9. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," SIGARCH Comput. Archit. News, vol. 31, no. 2, pp. 2-13, 2003.
10. J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Ch, S. Member, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in IEEE Journal Of Solid-State Circuits, 2002, pp. 1396-1402.
11. A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, and K. Roy, "Speed binning aware design methodology to improve profit under parameter variations," in ASP-DAC '06: Proceedings of the 2006 conference on Asia South Pacific design automation. Piscataway, NJ, USA: IEEE Press, 2006, pp. 712-717.
12. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, "Process variation in embedded memories: failure analysis and variation aware architecture," Solid-State Circuits, IEEE Journal of, vol. 40, no. 9, pp. 1804-1814, Sept. 2005.
13. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, "Modeling and testing of sram for new failure mechanisms due to process variations in nanoscale cmos," in VTS '05: Proceedings of the 23rd IEEE VLSI Test Symposium. Washington, DC, USA: IEEE Computer Society, 2005, pp. 292-297.
14. S. Narendra, A. Keshavarzi, B. Bloechel, S. Borkar, and V. De, "Forward body bias for microprocessors in 130-nm technology generation and beyond," Solid-State Circuits, IEEE Journal of, vol. 38, no. 5, pp. 696-701, May 2003.
15. H. Chang and S. S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," in DAC '05: Proceedings of the 42nd annual conference on Design automation. New York, NY, USA: ACM, 2005, pp. 523-528.
16. M. A. Hussain and M. Mutyam, "Block remap with turnoff: a variationtolerant cache design technique," in ASP-DAC '08: Proceedings of the 2008 conference on Asia and South Pacific design automation. Los Alamitos, CA, USA: IEEE Computer Society Press, 2008, pp. 783-788.
17. M. Mutyam and V. Narayanan, "Working with process variation aware caches," in DATE '07: Proceedings of the conference on Design, automation and test in Europe. San Jose, CA, USA: EDA Consortium, 2007, pp. 1152-1157.
18. S. Ozdemir, D. Sinha, G. Memik, J. Adams, and H. Zhou, "Yield-aware cache architectures," in MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2006, pp. 15-25.
19. P. Raghavan, J. Ayala, D. Atienza, F. Catthoor, G. De Micheli, and M. Lopez-Vallejo, "Reduction of register file delay due to process variability in vliw embedded processors," Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 121-124, May 2007.
20. X. Liang and D. Brooks, "Mitigating the impact of process variations on processor register files and execution units," in MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2006, pp. 504-514.
21. B. F. Romanescu, M. E. Bauer, S. Ozev, and D. J. Sorin, "Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching," in CF '08: Proceedings of the 2008 conference on Computing frontiers. New York, NY, USA: ACM, 2008, pp. 129-138.
22. D. Kannan, A. Shrivastava, S. Bhardwaj, and S. Vrudhul, "Power reduction of functional units considering temperature and process variations," in VLSID '08: Proceedings of the 21st International Conference on VLSI Design. Washington, DC, USA: IEEE Computer Society, 2008, pp. 533-539.
23. D. Kannan, A. Shrivastava, V. Mohan, S. Bhardwaj, and S. Vrudhula, "Temperature and process variations aware power gating of functional units," in VLSID '08: Proceedings of the 21st International Conference on VLSI Design. Washington, DC, USA: IEEE Computer Society, 2008, pp. 515-520.
24. R Development Core Team, R: A Language and Environment for Statistical Computing, R Foundation for Statistical Computing, Vienna, Austria, 2008, ISBN 3-900051-07-0. [Online]. Available: http://www.R-project.org
25. N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
26. Y.-F. Tsai, D. E. Duarte, N. Vijaykrishnan, and M. J. Irwin, "Characterization and modeling of run-time techniques for leakage power reduction," IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 11, pp. 1221-1232, 2004.
27. J. Fisher, "Trace scheduling: A technique for global microcode compaction," Computers, IEEE Transactions on, vol. C-30, no. 7, pp. 478-490, July 1981.
28. S. Muchnick, "Advanced compiler design and implementation," Morgan Kaufmann, 1997.
29. W.-M. W. Hwu, S. A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab, J. G. Holm, and D. M. Lavery, "The superblock: an effective technique for vliw and superscalar compilation," J. Supercomput., vol. 7, no. 1-2, pp. 229-248, 1993.
30. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann, "Effective compiler support for predicated execution using the hyperblock," SIGMICRO Newsl., vol. 23, no. 1-2, pp. 45-54, 1992.
31. J. Huck, D. Morris, J. Ross, A. Knies, H. Mulder, and R. Zahir, "Introducing the ia-64 architecture," IEEE Micro, vol. 20, no. 5, pp. 12-23, 2000.
32. M. Mutyam, F. Li, V. Narayanan, M. Kandemir, and M. J. Irwin, "Compiler-directed thermal management for vliw functional units," SIGPLAN Not., vol. 41, no. 7, pp. 163-172, 2006.