Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 292-297

  Chen, Qikai ^a   Mahmoodi, H ^a   Bhunia, S ^a   Roy, K ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

DFT; Failure mechanixm; March Test; Process Variation; SRAM

Indexed keywords

DFT; FAILURE MECHANISM; FAULT COVERAGES; MARCH TESTS; NANO-SCALE CMOS; PROCESS VARIATION; TEST TECHNIQUES; TEST TIME REDUCTION;

FAILURE (MECHANICAL); STATIC RANDOM ACCESS STORAGE; TESTING;

DESIGN FOR TESTABILITY;

EID: 84886474055     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.58     Document Type: Conference Paper

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