Temperature and process variations aware power gating of functional units

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Volumn , Issue , 2008, Pages 515-520

  Kannan, Deepa ^a   Shrivastava, Aviral ^a   Mohan, Vipin ^a   Bhardwaj, Sarvesh ^a   Vrudhula, Sarma ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CONSUMPTION; EXPONENTIAL INCREASE; FABRICATED CHIPS; FUNCTIONAL UNITS (FU); HIGH POWER DENSITY (HPD); INTERNATIONAL CONFERENCES; LEAKAGE POWER; LEAKAGE SENSOR; POWER CONSUMPTION (CE); POWER GATING; POWER GATING (PG); POWER REDUCTIONS; PROCESS VARIATIONS; PROCESSOR POWER CONSUMPTION; STANDARD DEVIATION (STD); TECHNOLOGY SCALING; VLSI DESIGNS;

DIGITAL SIGNAL PROCESSING; ENERGY POLICY; OPTICAL DESIGN; STANDARDS;

ELECTRIC POWER UTILIZATION;

EID: 47649120563     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.2008.83     Document Type: Conference Paper

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