ChipPower: An architecture-level leakage simulator

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2004, Pages 395-398

  Tsai, Yuh Fang ^a   Ankadi, Ananth Hegde ^a   Vijaykrishnan, N ^a   Irwin, Mary Jane ^a   Theocharides, Theo ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE LENGTH; LEAKAGE POWER; POWER BREAKDOWN; PROCESS VARIATIONS;

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC INVERTERS; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MOS DEVICES; SIMULATORS; STATIC RANDOM ACCESS STORAGE; THERMAL EFFECTS; THRESHOLD VOLTAGE;

POWER ELECTRONICS;

EID: 14844296421     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. H. Su, et al, "Full Chip Leakage Estimation Considering Power Supply and Temperature Variations", ISLPED'03, Aug. 2003,pp 78-83
2. W. Liao, et al, "Microarchitecture level power and thermal simulation considering temperature dependent leakage model", ISLPED'03. Aug. 2003, pp. 211-216
3. Trimaran tool-set, http://www.trimaran.org/
4. Intel Itanium, http://www.intel.com/products/server/processors/server/ itanium
5. Duarte, D, et al, "A Clock Power Model to Evaluate Impacts of Architectural and Technology Optimizations.", ITVLSI, Vol. 10, No. 6, Dec. 2002, pp. 844-855
6. Hot-Spot, http://www.lava.cs.virginia.edu/HotSpot
7. BSIM4.2.1, http://www-device.eecs.berkeley.edu/~bsim3/
8. S. Narendra, et al, "Full-Chip Sub-threshold Leakage Power Prediction and Reduction Techniques for sub-0.18 μm CMOS", IJSSC, Vol. 39, No. 2, Feb.'04, pp. 501-510