Working with process variation aware caches

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1152-1157

  Mutyam, Madhu ^a   Narayanan, Vijaykrishnan ^b  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION; PARAMETER ESTIMATION; PRODUCT DESIGN; TRANSISTORS;

DEEP-SUBMICRON DESIGNS; LATENCY VARIATIONS; PROCESS VARIATION; SET-LEVEL GRANULARITY;

BUFFER STORAGE;

EID: 34548354639     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364450     Document Type: Conference Paper

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