Reduction of register file delay due to process variability in VLIW embedded processors

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 121-124

  Raghavan, Praveen ^a   Ayala, José L ^b   Atienza, David ^c,d   Catthoor, Francky ^b   De Micheli, Giovanni ^d   López Vallejo, Marisa ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^d EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; EMBEDDED SYSTEMS; PROGRAM PROCESSORS;

PROCESS VARIABILITY; REGISTER FILE DELAY; SPEED VARIABILITY;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 34548847183     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378236     Document Type: Conference Paper

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