Block remap with turnoff: A variation-tolerant cache design technique

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 783-788

  Hussain, Mohammed Abid ^a   Mutyam, Madhu ^b  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ENERGY DISSIPATION; ENERGY POLICY; INDUSTRIAL ENGINEERING; TURNING;

ACCESS LATENCY; ASSOCIATIVITY; CACHE BLOCKING; CACHE DESIGNS; CHIP YIELD; DESIGN AUTOMATION CONFERENCE; DESIGN TECHNIQUES; FEATURE SIZES; HIGH-DENSITY; LEAKAGE ENERGIES; LOW-LATENCY; MEMORY COMPONENTS; ON-CHIP CACHES; ON-CHIP DATA CACHE; PERFORMANCE LOSSES; PROCESS VARIATIONS; SIMPLESCALAR; SOUTH PACIFIC; WORST-CASE DESIGN;

PROCESS ENGINEERING;

EID: 49649118364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484058     Document Type: Conference Paper

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