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Volumn , Issue , 2008, Pages 879-883

Reliability testing of through-silicon vias for high-current 3D applications

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS.; ELECTRONIC COMPONENTS; HIGH CURRENTS; VIA INTERCONNECTION;

EID: 51349126973     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550080     Document Type: Conference Paper
Times cited : (17)

References (8)
  • 1
    • 25844453501 scopus 로고    scopus 로고
    • Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection
    • Knickerbocker, J.U., et al, "Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection," IBM J. Res. Dev. 49 (4/5), 2005, pp. 725-754.
    • (2005) IBM J. Res. Dev , vol.49 , Issue.4-5 , pp. 725-754
    • Knickerbocker, J.U.1
  • 2
    • 61649110276 scopus 로고    scopus 로고
    • Three-dimensional Silicon Integration
    • submitted to
    • Knickerbocker, J.U., et al, "Three-dimensional Silicon Integration," submitted to IBM J.Res. Dev.
    • IBM J.Res. Dev
    • Knickerbocker, J.U.1
  • 3
    • 33845571282 scopus 로고    scopus 로고
    • A CMOS-compatible process for fabricating electrical through-vias in silicon
    • San Diego, CA, May
    • Andry, P.S., et al, "A CMOS-compatible process for fabricating electrical through-vias in silicon," Proc 56th Electronic Components and Technology Conf, San Diego, CA, May 2006, pp. 831-837.
    • (2006) Proc 56th Electronic Components and Technology Conf , pp. 831-837
    • Andry, P.S.1
  • 4
    • 51349083800 scopus 로고    scopus 로고
    • Design and fabrication of robust through-silicon vias
    • submitted to
    • Andry, P.S., et al, "Design and fabrication of robust through-silicon vias," submitted to IBM J. Res. Dev.
    • IBM J. Res. Dev
    • Andry, P.S.1
  • 5
    • 24644478268 scopus 로고    scopus 로고
    • Silicon carrier with deep through-vias, fine pitch wiring, and mrough cavity for parallel optical receiver
    • Lake Buena Vista, FL, May
    • Patel, C.S., et al, "Silicon carrier with deep through-vias, fine pitch wiring, and mrough cavity for parallel optical receiver," Proc 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, May 2005, pp. 1318-1324.
    • (2005) Proc 55th Electronic Components and Technology Conf , pp. 1318-1324
    • Patel, C.S.1
  • 6
    • 51349153897 scopus 로고    scopus 로고
    • CMOS-compatible silicon through-vias for 3D process integration
    • Boston MA
    • Tsang, C.K., et al, "CMOS-compatible silicon through-vias for 3D process integration," Proc. Mat. Res. Soc., Boston MA, 2006, pp. 145-153.
    • (2006) Proc. Mat. Res. Soc , pp. 145-153
    • Tsang, C.K.1
  • 7
    • 33845598091 scopus 로고    scopus 로고
    • Characterization of microbump C4 interconnets for Si-carrier SOP applications
    • San Diego, CA, May
    • Wright, S.L., et al, "Characterization of microbump C4 interconnets for Si-carrier SOP applications," Proc 56th Electronic Components and Technology Conf, San Diego, CA, May 2006, pp. 633-640.
    • (2006) Proc 56th Electronic Components and Technology Conf , pp. 633-640
    • Wright, S.L.1
  • 8
    • 35348909547 scopus 로고    scopus 로고
    • Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package
    • Reno, NV, May
    • Dang, B., et al, "Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package," Proc 57th Electronic Components and Technology Conf, Reno, NV, May 2007, pp. 42-48.
    • (2007) Proc 57th Electronic Components and Technology Conf , pp. 42-48
    • Dang, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.