Dopant-segregated schottky source/drain double-fate MOSFET design in the direct source-to-drain tunneling regime

IEEE Transactions on Electron Devices

Volumn 56, Issue 9, 2009, Pages 2016-2026

  Vega, Reinaldo A ^a   Liu, Kevin ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Direct source to drain tunneling (DSDT); Dopant segregation; Double gate; FinFET; Schottky barrier (SB); Ultrathin body

Indexed keywords

DIRECT SOURCE-TO-DRAIN TUNNELING (DSDT); DOPANT SEGREGATION; DOUBLE-GATE; FINFET; SCHOTTKY BARRIER (SB); ULTRATHIN BODY;

FIELD EFFECT TRANSISTORS; LOGIC DESIGN; MOSFET DEVICES; SCHOTTKY BARRIER DIODES; SEGREGATION (METALLOGRAPHY); SILICIDES; TUNNELING (EXCAVATION); WIND TUNNELS;

DOPING (ADDITIVES);

EID: 69549116131     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2026318     Document Type: Article

References (24)

1. H. Kawamura, T. Sakamoto, and T. Baba, "Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 76, no. 25, pp. 3810-3812, Jun. 2000.
2. J. R. Watling, A. Asenov, A. R. Brown, A. Svizhenko, and M. P. Anantram, "Direct source to drain tunnelling and its impact on the intrinsic parameter fluctuations in nanometer scale double gate MOSFETs," in Proc. Nanotech, 2003, vol. 2, pp. 202-205.
3. M. Bescond, J. L. Autran, D. Munteanu, N. Cavassilas, and M. Lanoo, "Atomic-scale modeling of source-to-drain tunneling in ultimate Schottky barrier double-gate MOSFETs," in Proc. 33rd Conf. Eur. Solid-State Device Res., 2003, pp. 395-398.
4. K. D. Cantley, Y. Liu, H. S. Pal, T. Low, S. S. Ahmed, and M. S. Lundstrom, "Performance analysis of III-V materials in a double-gate nano-MOSFET," in IEDM Tech. Dig., 2007, pp. 113-116.
5. Q. Rafhay, R. Clerc, G. Ghibaudo, and G. Pananakakis, "Impact of source-to-drain tunnelling on the scalability of arbitrary oriented alternative channel material nMOSFETs," Solid State Electron., vol. 52, no. 10, pp. 1474-1481, Oct. 2008.
6. User's Manual for Sentaurus Device, Synopsys Co., Mountain View, CA, 2007.
7. R. A. Vega and T.-J. King Liu, "A comparative study of dopant-segregated schottky and raised source/drain double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2665-2677, Oct. 2008.
8. R. A. Vega and T.-J. King Liu, "Three-dimensional FinFET source/drain and contact design optimization study," IEEE Trans. Electron Devices vol. 56, no. 7, pp. 1483-1492, Jul. 2009.
9. International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: http://public.itrs.net
10. R. Venugopal, Z. Ren, and M. S. Lundstrom, "Simulating quantum transport in nanoscale MOSFETs: Ballistic hole transport, subband engineering and boundary conditions," IEEE Trans. Nanotechnol., vol. 2, no. 3, pp. 125-143, Sept. 2003.
11. H. Lee, L.-E. Yu, S.-W. Ruy, J.-W. Han, K. Jeon, D.-Y. Jang, K.-H. Kim, J. Lee, J.-H. Kim, S. C. Jeon, G. S. Lee, J. S. Oh, Y. C. Park, W. H. Bae, H. M. Lee, J. M. Yang, J. J. Yoo, S. I. Kim, and Y.-K. Choi, "Sub-5 nm all-around gate FinFET for ultimate scaling," in VLSI Symp. Tech. Dig., 2006, pp. 58-59.
12. N. Mise, S. Migita, Y. Watanabe, H. Satake, T. Nabatame, and A. Toriumi, "(111)-faceted metal source and drain for aggressively scaled metal/ high-k MISFETs," IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1244-1249, May 2008.
13. T.-Y. Liow, K.-M. Tan, R. T. P. Lee, M. Zhu, B. L.-H. Tan, G. S. Samudra, N. Balasubramanian, and Y.-C. Yeo, "5 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free melt-enhanced dopant (MeltED) diffusion and activation technique," in Proc. VLSI Technol., 2008, pp. 36-37.
14. K. Shenai, E. Sangiorgi, R. M. Swanson, K. C. Saraswat, and R. W. Dutton, "Modeling and characterization of dopant redistributions in metal and silicide contacts," IEEE Trans. Electron Devices, vol. ED-32, no. 4, pp. 793-799, Apr. 1985.
15. M. Ono, A. Nishiyama, andM. Koyama, "Degradation of current drivability of Schottky barrier source/drain transistors induced by high-k gate dielectrics and possible measures to suppress the phenomenon," Solid State Electron., vol. 50, no. 5, pp. 788-794, May 2006.
16. T. Miyashita, K. Ikeda, Y. S. Kim, T. Yamamoto, Y. Sambonsugi, H. Ochimizu, T. Sakoda, M. Okuno, H. Minakata, H. Ohta, Y. Hayami, K. Ookoshi, Y. Shimamune, M. Fukuda, A. Hatada, K. Okabe, T. Kubo, M. Tajima, T. Yamamoto, E. Motoh, T. Owada, M. Nakamura, H. Kudo, T. Sawada, J. Nagayama, A. Satoh, T. Mori, A. Hasegawa, H. Kurata, K. Sukegawa, A. Tsukune, S. Yamaguchi, K. Ikeda,M. Kase, T. Futatsugi, S. Satoh, and T. Sugii, "High-performance and low-power bulk logic platform utilizing FET specific multiple-stressors with highly enhanced strain and full-porous low-k interconnects for 45-nm CMOS technology," in IEDM Tech. Dig., 2007, pp. 251-254.
17. A. B. Sachid, R. Francis, M. S. Baghini, D. K. Sharma, K.-H. Bach, R. Mahnkopf, and V. R. Rao, "Sub-20 nm gate length FET Design: Can high-k spacers make a difference?" in IEDM Tech. Dig., 2008, pp. 697-700.
18. R. A. Vega, "Schottky field effect transistors and Schottky CMOS circuitry," M.S. thesis, Dept. Microelectron. Eng., Rochester Inst. Technol., Rochester, NY, 2006.
19. X. Chen, S. Samavedam, V. Narayanan, K. Stein, C. Hobbs, C. Baiocco, W. Li, D. Jaeger, M. Zaleski, H. S. Yang, N. Kim, Y. Lee, D. Zhang, L. Kang, J. Chen, H. Zhuang, A. Sheikh, J. Wallner, M. Aquilino, J. Han, Z. Jin, J. Li, G. Massey, S. Kalpat, R. Jha, N. Moumen, R. Mo, S. Kirshnan, X. Wang, M. Chudzik, M. Chowdhury, D. Nair, C. Reddy, Y. W. Teh, C. Kothandaraman, D. Coolbaugh, S. Pandey, D. Tekleab, A. Thean, M. Sherony, C. Lage, J. Sudijono, R. Lindsay, J. H. Ku, M. Khare, and A. Steegen, "A cost effective 32 nm high-k/metal gate CMOS technology for low power applications with single-metal/gate-first process," in Proc. VLSI Technol., 2008, pp. 88-89.
20. t CMOS featuring La/Al-doped HfSiO/TaC and 10 ps invertor delay," in Proc. VLSI Technol., 2008, pp. 130-131.
21. C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, and C. Wiegand, "45 nm high-k + metal gate strain-enhanced transistors," in Proc. VLSI Technol., 2008, pp. 128-129.
22. Q. Chen, L. Wang, and J. D. Meindl, "Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs," Solid State Electron., vol. 49, no. 2, pp. 271-274, Feb. 2005.
23. H. Dagour, K. Endo, V. De, and K. Banerjee, "Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability," in IEDM Tech. Dig., 2008, pp. 705-708.
24. Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, Mar. 2002.