(111)-Faceted metal source and drain for aggressively scaled metal/ high-k MISFETs

IEEE Transactions on Electron Devices

Volumn 55, Issue 5, 2008, Pages 1244-1249

  Mise, Nobuyuki ^a,b   Migita, Shinji ^a   Watanabe, Yukimune ^a   Satake, Hideki ^a   Nabatame, Toshihide ^a   Toriumi, Akira ^c  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

^b SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

Epitaxial metal source and drain (S D); High k gate dielectric; Metal gate; Nickel disilicide; Short channel effect (SCE)

Indexed keywords

ELECTRODES; GATE DIELECTRICS; NICKEL COMPOUNDS; SCHOTTKY BARRIER DIODES; SEMICONDUCTING SILICON;

EPITAXIAL METAL; FULLY SILICIDED GATE ELECTRODE; HIGH-K GATE DIELECTRIC; METAL GATE; NICKEL DISILICIDE; SHORT-CHANNEL EFFECT (SCE);

MISFET DEVICES;

EID: 43749106255     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.918408     Document Type: Article

References (17)

1. H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, "Sub-10-nm planar-bulk-CMOS devices using lateral junction control," in IEDM Tech. Dig., 2003, pp. 989-991.
2. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller H.-S. P. Wong, and W. Haensch, "Extreme scaling with ultra-thin Si channel MOSFETs," in IEDM Tech. Dig., 2002, pp. 267-270.
3. N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Mizuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaba, M. Takayanagi, K. Ishimaru, and H. Ishiuchi, "A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices," in VLSI Symp. Tech. Dig., 2004, pp. 84-85.
4. N. Mise, Y. Watanabe, S. Migita, T. Nabatame, H. Satake, and A. Toriumi, "Self-aligned FUSI engineered (SUSIE) ultra-thin SOI CMOS with fast lateral silicidation and reaction edge segregation," in Proc. Silicon Nanoelectronics Workshop, 2005, p. 16.
5. 2 (111)-facetted full silicide source/drain," in Proc. Device Res. Conf. Dig., 2005, pp. 197-198.
6. 2 source/drain on short channel effect and line edge roughness in extremely scaled MOSFETs," in Proc. ISDRS, 2005, pp. 111-112.
7. 2 source and drain for advanced SOI MOSFETs," in Proc. Int. Workshop Junction Technol., Shanghai, China, 2006, pp. 170-175.
8. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," in IEDM Tech. Dig., 2000, pp. 57-60.
9. S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, "N-type Schottky barrier source/drain MOSFET using ytterbium silicide," IEEE Electron Device Lett., vol. 25, no. 8, pp. 565-567, Aug. 2004.
10. B.-Y. Tsui and C.-P. Lin, "A novel 25-nm modified Schottky-barrier FinFET with high performance," IEEE Electron Device Lett., vol. 25, no. 6, pp. 430-432, Jun. 2004.
11. A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, "Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with Dopant segregation technique," in VLSI Symp. Tech. Dig., 2004, pp. 168-169.
12. S. M. Sze, Physics of Semiconductor Devices, pp. 304-307. ISBN 0-471-05661-8.
13. T. Ichimori and N. Hirashita, "Fully-depleted SOI CMOSFETs with the fully-silicided source/drain structure," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2296-2300, Dec. 2002.
14. K. Maex and M. van Rossum, Properties of Metal Silicides. London, U.K.: INSPFC, 1995.
15. x film formation for MOSCAPs and nMOSFETs through layer-by-layer deposition and annealing process," in VLSI Symp. Tech. Dig., 2003, pp. 25-26.
16. T. Wada and N. Kotani, "Design and development of 3-dimensional process simulator," IEICE Trans. Electron., vol. E82-C, no. 6, pp. 839-847, 1999.
17. [Online]. Available: Http://www.tcad-international.com/HyDeLEOS_e.html