Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 7, 2009, Pages 1427-1440

  Hwang, Myeong Eun ^a   Jung, Seong Ook ^b   Roy, Kaushik ^c  

^a INTEL CORPORATION   (United States)

^b Yonsei University   (South Korea)

^c Purdue University   (United States)

Author keywords

CMOS logic; Gate delay; Interconnect delay; Logical effort; Signal slope

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTS; SPICE; TIMING CIRCUITS;

ACCURATE ESTIMATION; BENCHMARK CIRCUIT; CMOS LOGIC; DYNAMIC BEHAVIORS; GATE DELAYS; INTERCONNECT DELAY; LOGICAL EFFORT; THREE ORDERS OF MAGNITUDE;

DELAY CIRCUITS;

EID: 67651156228     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2006217     Document Type: Article

References (33)

1. J. Keane, H. Eom, T. H. Kim, S. Sapatnekar, and C. Kim, "Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing," in Proc. ACM/IEEE DAC, Jul. 2006, pp. 425-428.
2. A. Kabbani, D. Al-Khalili, and A. J. Al-Khalili, "Delay analysis of CMOS gates using modified logical effort model," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 6, pp. 937-947, Jun. 2005.
3. I. Sutherland, B. Sproull, and D. Harries, Logical Effort: Design Fast CMOS Circuits. San Mateo, CA: Morgan Kaufmann, Jan. 1999.
4. T. Sakurai and A. R. Newton, "Delay analysis of series-connected MOSFET circuits," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122-131, Feb. 1991.
5. H. Im, T. Inukai, H. Gomyo, T. Hiramoto, and T. Sakurai, "VTCMOS characteristics and its optimum conditions predicted by a compact analytical model," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. 11, no. 5, pp. 755-761, Oct. 2003.
6. J. L. Rossello and J. Segura, "An analytical charge-based compact delay model for submicrometer CMOS inverters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1301-1311, Jul. 2004.
7. A. Hirata, H. Onodera, and K. Tamura, "Estimation of propagation delay considering short-circuit current for static CMOS gates," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 11, pp. 1194-1198, Nov. 1998.
8. A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, "A modeling technique for CMOS gates," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 5, pp. 557-575, May 1999.
9. The International Technology Roadmap for Semiconductors 2003 [Online]. Available: http://public.itrs.net/
10. C. Maxfield, Designus Maximus Unleashed. Boston, MA: Newnes, Mar. 1998, ch. 25.
11. W. C. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, no. 1, pp. 55-63, Jan. 1948.
12. S. Y. Kim and S. S. Wong, "Closed-form RC and RLC delay models considering input rise time," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp. 2001-2010, Sep. 2007.
13. R. Mita, G. Palumbo, and M. Poli, "Propagation delay of an RC-chain with a ramp input," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 1, pp. 66-70, Jan. 2007.
14. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 9, no. 4, pp. 352-366, Apr. 1990.
15. C. L. Ratzlaff, N. Gopal, and L. T. Pillage, "RICE: Rapid interconnect circuit evaluator," in Proc. ACM/IEEE DAC, 1991, pp. 555-560.
16. J. Sun, Y. Zheng, Q. Ye, and T. Ye, "Interconnect delay and slew metrics using the first three moments," in Proc. IEEE ISQED, Mar. 2005 pp. 598-602.
17. J. M. Daga and D. Auvergne, "A comprehensive delay macro modeling for submicrometerCMOSlogics," IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 42-55, Jan. 1999.
18. R. Arunachalam, F. Dartu, and L. T. Pileggi, "CMOS gate delay models for general RLC loading," in Proc. IEEE ICCD, Oct. 1997, pp. 224-229.
19. F. Dartu and L. T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," in Proc. ACM/IEEE DAC, Jun. 1997, pp. 46-51.
20. K. T. Tang and E. G. Friedman, "Delay and power expressions characterizing a CMOS inverter driving an RLC load," in Proc. IEEE ISCAS, May 2000, vol. 3, pp. 283-286.
21. F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 5, pp. 544-553, May 1996.
22. L. K. Vakati and J. Wang, "A new multi-ramp driver model with RLC interconnect load," in Proc. IEEE ISCAS, May 2004, vol. 5, pp. 269-272.
23. J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
24. M.-E. Hwang, S.-O. Jung, and K. Roy, "Slope interconnect effort: Gate-interconnect interdependent delay model for CMOS logic gates with scaled supply voltage," in Proc. IEEE ISLPED, Portland, OR, Aug. 2007, pp. 387-390.
25. M.-E. Hwang, T. Cakici, and K. Roy, "Process-tolerant β-ratio modulation for ultra-dynamic voltage scaling," in Proc. ACM/IEEE DATE, Apr. 2007, pp. 1550-1555.
26. M.-E. Hwang, K. Kim, A. Raychowdhury, and K. Roy, "A 85 mV 40 nW process tolerant 8 × 8 FIR filter with ultra-dynamic voltage scaling," in Proc. IEEE VLSI Circuit Symp., Kyoto, Japan, Jun. 2007, pp. 154-155.
27. A. B. Kahng, K. Masuko, and S. Muddu, "Analytical delay models for VLSI interconnects under ramp input," in Proc. IEEE/ACM ICCAD, Nov. 1996, pp. 30-36.
28. A. B. Kahng and S. Muddu, "Improved effective capacitance computations for use in logic and layout optimization," in Proc. 12th Int. Conf. VLSI Design, 1999, pp. 578-582.
29. S. Abbaspour and M. Pedram, "Calculating the effective capacitance for the RC interconnect in VDSM technologies," in Proc. ACM/IEEE ASP-DAC Jan. 2003, pp. 43-48.
30. J. D. Ma and R. A. Rutenbar, "Fast interval-valued statistical modeling of interconnect and effective capacitance," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 710-724, Apr. 2006.
31. C. Guoqing and E. G. Friedman, "Effective capacitance of inductive interconnects for short-circuit power analysis," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 1, pp. 26-30, Jan. 2008.
32. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003, ch. 4.
33. Bsim4.6.1 MOSFET Model-User's Manual Online. Available: http:// www-device.eecs.berkeley.edu/bsim3/bsim4_get.html