A modeling technique for CMOS gates

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 5, 1999, Pages 557-575

  Chatzigeorgiou, Alexander ^a   Nikolaidis, Spiridon ^a   Tsoukalas, Loannis ^a  

^a ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

CMOS gates; Modeling; Simulation; Timing analysis

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; SEMICONDUCTOR DEVICE MODELS; TIME DOMAIN ANALYSIS;

TIMING SIMULATORS;

GATES (TRANSISTOR);

EID: 0032668258     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.759070     Document Type: Article

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