Effective capacitance of inductive interconnects for short-circuit power analysis

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 1, 2008, Pages 26-30

  Chen, Guoqing ^a   Friedman, Eby G ^b  

^a INTEL CORPORATION   (United States)

^b University of Rochester   (United States)

Author keywords

Interconnect; RLC; Shielding effect; Short circuit power

Indexed keywords

CIRCUIT SIMULATION; SHIELDING; TABLE LOOKUP; TIMING CIRCUITS;

EFFECTIVE CAPACITANCE; INTERCONNECT; INTERCONNECT RESISTANCE; LOAD CAPACITANCE; SHIELDING EFFECT; SHORT-CIRCUIT POWER; SPECTRE SIMULATIONS; VOLTAGE TRANSITION;

CAPACITANCE;

EID: 64749088135     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.907812     Document Type: Article

References (16)

1. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Dynamic and short-circuit power of CMOS gates driving lossless transmission lines," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 8, pp. 950-961, Aug. 1999.
2. H. J. M. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 468-473, Aug. 1984.
3. L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, "Propagation delay and short-circuit power dissipation modeling of CMOS inverter," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 3, pp. 259-270, Mar. 1998.
4. K. Nose and T. Sakurai, "Analysis and future trend of short-circuit power," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.s, vol. 19, no. 9, pp. 1023-1030, Sep. 2000.
5. M. Mondal, S. Kirolos, and Y. Massoud, "Estimation of capacitive crosstalk-induced short-circuit energy," in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp. 897-900.
6. A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, "Modeling CMOS gates driving RC interconnect loads," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 4, pp. 4134-18, Apr. 2001.
7. F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst.s, vol. 15, no. 5, pp. 544-553, May 1996.
8. J. L. Rosselló and J. Segura, "A simple power consumption model of CMOS buffers driving RC interconnect lines," in Proc. Int. Workshop Power and Timing Modeling Optimization and Simulation, Sep. 2001, pp. 4.2.1-4.2.10.
9. M. A. El-Moursy and E. G. Friedman, "Shielding effect of on-chip interconnect inductance," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 3, pp. 396-400, Mar. 2005.
10. G. Chen and E. G. Friedman, "Effective capacitance of RLC loads for estimating short-circuit power," in Proc. IEEE Int. Symp. Circuits Syst.s, May 2006, pp. 2065-2068.
11. P. R. O'Brien and T. L. Savarino, "Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Apr. 1989, pp. 512-515.
12. X. Yang, X. Yang, C. K. Cheng, W. H. Ku, and R. J. Carragher, "Hurwitz stable reduced order modeling for RLC interconnect trees," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Nov. 2000, pp. 222-228.
13. G. Chen and E. G. Friedman, "An RLC interconnect model based on Fourier analysis," IEEE Trans. Comput.-Aided Design of Integrated Circuits Syst.s, vol. 24, no. 2, pp. 170-183, Feb. 2005.
14. J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
15. Berkeley Predictive Technology Model, Univ. California, Berkeley, Jul. 2002 [Online]. Available: http://www-device.eecs.berkeley.edu/~ptm
16. Q. Wang and S. B. K. Vrudhula, "A new short circuit power model for complex CMOS gates," in Proc. IEEE Alessanfro Volta Memorial Workshop Low-Power Design, Mar. 1999, pp. 98-106.