Delay analysis of CMOS gates using modified logical effort model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 6, 2005, Pages 937-947

  Kabbani, A ^a   Al Khalili, D ^b   Al Khalili, A J ^c  

^a RYERSON UNIVERSITY   (Canada)

^b ROYAL MILITARY COLLEGE OF CANADA   (Canada)

^c Dept of Electrical and Computer Engineering   (Canada)

Author keywords

CMOS; Delay model; DSM; Logic gates; Logical effort

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ERROR ANALYSIS; GATES (TRANSISTOR); MATHEMATICAL MODELS; MOSFET DEVICES; SWITCHING SYSTEMS;

CMOS GATES; DELAY ANALYSIS; DELAY MODELS; DSM; LOGICAL EFFORT; MODIFIED LOGICAL EFFORT (MLE);

CMOS INTEGRATED CIRCUITS;

EID: 20444470600     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.847892     Document Type: Article

References (19)

1. K. Scott and K. Keutzer, "Improving cell libraries for synthesis," in Proc. IEEE Custom Integr. Circuits Conf., 1994, pp. 128-131.
2. A. I. Reis, R. Reis, and M. Robert, "Library free technology mapping," in Proc. Int. Conf. VLSI, 1997, pp. 303-314.
3. A. Reis, M. Robert, and R. Ries, "Topological parameters for library free technology mapping," in Proc. IEEE 11th Brazilian Symp. Integr. Circuit Design, 1998, pp. 213-216.
4. F. Moraes, M. Robert, and D. Auvergne, "A virtual CMOS library approach for fast layout synthesis," in Proc. 10th IFIP Int. Conf. VLSI, 1999, pp. 415-426.
5. K. Keutzer, K. Wolf, J. Maxey, D. Pietromonaco, J. Lewis, M. Lefebvre, and J. Burns, "PANEL: Cell libraries build vs. buy; static vs. dynamic," in Proc. 36th IEEE/ACM Design Automation Conf., 1999, pp. 341-342.
6. T. Sakurai and R. Newton, "Delay analysis of series-connected MOSFET circuits," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122-131, Feb. 1991.
7. _, "A simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFETs," in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 105-108.
8. K. Shakeri and J. D. Meindl, "A compact delay model for series-connected MOSFETs," in Proc. IEEE GLSVLSI, 2002, pp. 37-40.
9. A. Hirata, H. Onodera, and K. Tamaru, "Proposal of a timing model for CMOS logic gates driving a CRC load," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 537-544.
10. A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, "A modeling technique for CMOS gates," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 18, no. 5, pp. 557-575, May 1999.
11. J. Michel and D. Auvergne, "A comprehensive delay macro modeling for submicrometer CMOS logics," IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 42-55, Jan. 1999.
12. I. Sutherland, B. Sproull, and D. Harries, Logical effort: Design Fast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, Jan. 1999.
13. M. John and S. Smith, Application-Specific Integrated Circuits. Reading, MA: Addison-Wesley, 1997.
14. J. P. Uyemura, CMOS Circuit Logic Design. Norwell, MA: Kluwer, 1999.
15. K. Y. Toh, P. K. Ko, and R. G. Meyer, "An engineering model for short channel MOS devices," IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 950-958, Aug. 1988.
16. K. S. Yeo, S. S. Rofail, and W. L. Goh, CMOS/BiCMOS VLSI, Low Voltage Low Power. Englewood Cliffs, NJ: Prentice-Hall, 2002.
17. S. S. Rofail and K. S. Yeo, "Experimentally based analytical model for deep-submicron LDD PMOSFETs in a Bi-MOS hybrid-mode environment," IEEE Trans. Electron Dev., vol. 44, no. 9, pp. 1473-1482, Sep. 1997.
18. Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User's Guide. Norwell, MA: Kluwer, 1999.
19. B. J. Sheu, D. L. Scharfetter, P.-K. Ko, andM.-C. Jeng, "BSIM: Berkeley short-channel IGFET model for MOS transistors," IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 558-565, Aug. 1987.