Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 387-390

  Hwang, Myeong Eun ^a   Jung, Seong Ook ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b Yonsei University   (South Korea)

Author keywords

Gate delay; Interconnect; Signal slope; Subthreshold operation

Indexed keywords

CIRCUIT DELAY; GATE DELAY; SIGNAL SLOPE; SUBTHRESHOLD OPERATION; SUPPLY VOLTAGE;

CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; MATHEMATICAL MODELS;

LOGIC GATES;

EID: 36949032904     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283865     Document Type: Conference Paper

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