Improved effective capacitance computations for use in logic and layout optimization

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 578-582

  Kahng, Andrew B ^a   Muddu, Sudhakar ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COMPUTER SOFTWARE; ERROR ANALYSIS; LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION;

INTERCONNECT LOADS; SOFTWARE PACKAGE HSPICE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032715195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745217     Document Type: Conference Paper

References (15)