Closed-form RC and RLC delay models considering input rise time

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 9, 2007, Pages 2001-2010

  Kim, So Young ^a,b   Wong, S Simon ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Delay model; Inductance; Interconnect; Ramp input; Resistive shielding

Indexed keywords

CAPACITANCE; DELAY CIRCUITS; INDUCTANCE; INTERCONNECTION NETWORKS; OPTIMIZATION;

CLOSED-FORM DELAY FORMULAS; EFFECTIVE DISTANCE CORRECTION FACTOR; ELMORE DELAY MODEL; RESISTIVE SHIELDING;

INTEGRATED CIRCUITS;

EID: 34648831866     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.902539     Document Type: Article

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